ROM (Read-Only Memory) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a ROM module with input address and output data.

Verilog

module rom(input [3:0] addr, output reg [7:0] data);
  always @(*) begin
    case([1])
      4'd0: data = 8'hA1;
      4'd1: data = 8'hB2;
      default: data = 8'h00;
    endcase
  end
endmodule

Drag options to blanks, or click blank then click option'

Adata

Baddr

Cinput

Doutput

Attempts:

3 left

💡 Hint

Common Mistakes

Using the output signal instead of the address in the case statement.

Forgetting to use the input address signal.

The case statement uses the input address addr to select the ROM data.

2fill in blank

medium

Complete the code to initialize the ROM contents using a Verilog array.

Verilog

reg [7:0] rom_mem [0:15];
initial begin
  rom_mem[0] = 8'h1A;
  rom_mem[1] = 8'h2B;
  rom_mem[2] = 8'h3C;
  rom_mem[3] = 8'h4D;
  // ... other initializations
end

always @(*) begin
  data = [1];
end

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Arom_mem[addr]

Brom_mem[data]

Crom_mem[0]

Drom_mem[15]

Attempts:

3 left

💡 Hint

Common Mistakes

Indexing the ROM memory with the output signal instead of the address.

Using a fixed index instead of the variable address.

The output data is assigned from the ROM memory at the given address addr.

3fill in blank

hard

Fix the error in the ROM read logic to correctly assign data asynchronously.

Verilog

always @([1]) begin
  data = rom_mem[addr];
end

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Aposedge clk

Bnegedge clk

Caddr

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edges in sensitivity list for asynchronous ROM read.

Leaving sensitivity list empty or incorrect.

The ROM output should update whenever the address changes, so the sensitivity list must include addr.

4fill in blank

hard

Fill both blanks to create a ROM module with parameterized data width and depth.

Verilog

module rom #(parameter WIDTH = [1], DEPTH = [2]) (
  input [$clog2(DEPTH)-1:0] addr,
  output reg [WIDTH-1:0] data
);
  reg [WIDTH-1:0] mem [0:DEPTH-1];
  always @(*) begin
    data = mem[addr];
  end
endmodule

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A8

B16

C256

D1024

Attempts:

3 left

💡 Hint

Common Mistakes

Using invalid parameter values that don't match the address width.

Mixing up WIDTH and DEPTH values.

The data width is set to 8 bits and the depth to 256 locations, common ROM sizes.

5fill in blank

hard

Fill all three blanks to implement a ROM with synchronous read using a clock.

Verilog

module rom_sync(
  input clk,
  input [3:0] addr,
  output reg [7:0] data
);
  reg [7:0] mem [0:15];
  always @(posedge [1]) begin
    data <= mem[[2]];
  end
endmodule

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Aclk

Baddr

Cdata

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using the wrong signal in the sensitivity list.

Indexing memory with the output data signal.

The synchronous ROM reads data on the rising edge of the clock clk, using the address addr to index memory.

Practice

1. What is the primary purpose of a ROM (Read-Only Memory) in Verilog?

easy

A. To store fixed data that cannot be changed during simulation or operation

B. To store data that can be written and read dynamically

C. To perform arithmetic operations

D. To generate clock signals

Solution

1. Step 1: Understand ROM functionality

   ROM is designed to hold data that is fixed and cannot be modified during operation.

2. Step 2: Compare with other memory types

   Unlike RAM, ROM data is read-only and does not support writing during runtime.

3. Final Answer:

   To store fixed data that cannot be changed during simulation or operation -> Option A

4. Quick Check:

   ROM = fixed data storage [OK]

Hint: ROM stores fixed data only, no writes allowed [OK]

Common Mistakes:

• Confusing ROM with RAM (read-write memory)
• Thinking ROM can perform operations
• Assuming ROM generates signals

2. Which of the following is the correct way to declare a ROM using an array and initial block in Verilog?

easy

A. integer rom_mem; always @(posedge clk) rom_mem = 8'hAA;

B. wire [7:0] rom_mem [0:3]; always @(posedge clk) rom_mem[0] <= 8'hAA;

C. reg [7:0] rom_mem; initial rom_mem = 8'hAA;

D. reg [7:0] rom_mem [0:3]; initial begin rom_mem[0] = 8'hAA; rom_mem[1] = 8'hBB; rom_mem[2] = 8'hCC; rom_mem[3] = 8'hDD; end

Solution

1. Step 1: Identify correct ROM declaration

   ROM is declared as a reg array with an initial block to assign fixed values.

2. Step 2: Check each option

   reg [7:0] rom_mem [0:3]; initial begin rom_mem[0] = 8'hAA; rom_mem[1] = 8'hBB; rom_mem[2] = 8'hCC; rom_mem[3] = 8'hDD; end uses reg array and initial block correctly. wire [7:0] rom_mem [0:3]; always @(posedge clk) rom_mem[0] <= 8'hAA; uses wire and always block incorrectly. Options C and D do not declare arrays properly.

3. Final Answer:

   reg [7:0] rom_mem [0:3]; initial begin rom_mem[0] = 8'hAA; rom_mem[1] = 8'hBB; rom_mem[2] = 8'hCC; rom_mem[3] = 8'hDD; end -> Option D

4. Quick Check:

   ROM array + initial block = reg [7:0] rom_mem [0:3]; initial begin rom_mem[0] = 8'hAA; rom_mem[1] = 8'hBB; rom_mem[2] = 8'hCC; rom_mem[3] = 8'hDD; end [OK]

Hint: Use reg array with initial block for ROM data [OK]

Common Mistakes:

• Using wire instead of reg for ROM array
• Assigning inside always block for ROM
• Not using an array for multiple ROM entries

3. Given the following Verilog ROM code, what is the output value of data_out when addr = 2'b10?

module rom_example(input [1:0] addr, output reg [7:0] data_out);
  always @(*) begin
    case(addr)
      2'b00: data_out = 8'h1A;
      2'b01: data_out = 8'h2B;
      2'b10: data_out = 8'h3C;
      2'b11: data_out = 8'h4D;
      default: data_out = 8'h00;
    endcase
  end
endmodule

medium

A. 8'h4D

B. 8'h1A

C. 8'h3C

D. 8'h00

Solution

1. Step 1: Locate the case for addr = 2'b10

   The case statement assigns data_out = 8'h3C when addr is 2'b10.

2. Step 2: Confirm output value

   Since addr matches 2'b10, data_out will be 8'h3C.

3. Final Answer:

   8'h3C -> Option C

4. Quick Check:

   addr 2'b10 -> data_out 8'h3C [OK]

Hint: Match addr in case to find data_out quickly [OK]

Common Mistakes:

• Choosing wrong case label
• Confusing hex values
• Ignoring default case

4. Identify the error in this ROM Verilog code snippet:

module rom_bug(input [1:0] addr, output reg [7:0] data_out);
  reg [7:0] rom_mem [0:3];
  initial begin
    rom_mem[0] = 8'hAA;
    rom_mem[1] = 8'hBB;
    rom_mem[2] = 8'hCC;
    rom_mem[3] = 8'hDD;
  end
  always @(*) begin
    data_out = rom_mem[addr];
  end
endmodule

medium

A. ROM array should be declared as wire, not reg

B. No error; code correctly implements ROM

C. Initial block cannot be used for ROM initialization

D. Using addr as index without conversion causes error

Solution

1. Step 1: Check ROM declaration and initialization

   ROM is declared as reg array and initialized in initial block, which is correct for simulation.

2. Step 2: Verify data output assignment

   Using addr as index to read rom_mem is valid and data_out is assigned in combinational always block.

3. Final Answer:

   No error; code correctly implements ROM -> Option B

4. Quick Check:

   ROM reg array + initial + combinational read = correct [OK]

Hint: ROM uses reg array + initial block + combinational read [OK]

Common Mistakes:

• Thinking initial block is illegal for ROM
• Confusing reg and wire for ROM arrays
• Assuming addr needs conversion

5. You want to implement a 4-word ROM in Verilog that outputs the square of the address value (0, 1, 4, 9). Which of the following code snippets correctly implements this ROM?

hard

A. always @(addr) begin case(addr) 2'b00: data_out=8'd0; 2'b01: data_out=8'd1; 2'b10: data_out=8'd4; 2'b11: data_out=8'd9; default: data_out=8'd0; endcase end

B. reg [7:0] rom [0:3]; initial begin rom[0]=8'd0; rom[1]=8'd1; rom[2]=8'd4; rom[3]=8'd9; end always data_out = rom[addr];

C. reg [7:0] rom [0:3]; assign rom[0]=0; assign rom[1]=1; assign rom[2]=4; assign rom[3]=9; assign data_out=rom[addr];

D. reg [7:0] rom [0:3]; always @(posedge clk) begin rom[0]<=0; rom[1]<=1; rom[2]<=4; rom[3]<=9; end assign data_out=rom[addr];

Solution

1. Step 1: Analyze each code snippet for ROM implementation

   reg [7:0] rom [0:3]; initial begin rom[0]=8'd0; rom[1]=8'd1; rom[2]=8'd4; rom[3]=8'd9; end always @(*) data_out = rom[addr]; lacks module and always block structure; data_out assignment is incomplete. always @(addr) begin case(addr) 2'b00: data_out=8'd0; 2'b01: data_out=8'd1; 2'b10: data_out=8'd4; 2'b11: data_out=8'd9; default: data_out=8'd0; endcase end uses a case statement to output fixed squares based on addr, which is a valid ROM implementation. reg [7:0] rom [0:3]; assign rom[0]=0; assign rom[1]=1; assign rom[2]=4; assign rom[3]=9; assign data_out=rom[addr]; tries to assign values to wire array elements, which is illegal. reg [7:0] rom [0:3]; always @(posedge clk) begin rom[0]<=0; rom[1]<=1; rom[2]<=4; rom[3]<=9; end assign data_out=rom[addr]; tries to assign ROM values inside a clocked always block, which is not suitable for ROM initialization.

2. Step 2: Confirm correct ROM behavior

   always @(addr) begin case(addr) 2'b00: data_out=8'd0; 2'b01: data_out=8'd1; 2'b10: data_out=8'd4; 2'b11: data_out=8'd9; default: data_out=8'd0; endcase end correctly outputs squares for each address using a combinational case statement, matching ROM behavior.

3. Final Answer:

   always @(addr) begin case(addr) 2'b00: data_out=8'd0; 2'b01: data_out=8'd1; 2'b10: data_out=8'd4; 2'b11: data_out=8'd9; default: data_out=8'd0; endcase end -> Option A

4. Quick Check:

   ROM as combinational case statement = always @(addr) begin case(addr) 2'b00: data_out=8'd0; 2'b01: data_out=8'd1; 2'b10: data_out=8'd4; 2'b11: data_out=8'd9; default: data_out=8'd0; endcase end [OK]

Hint: Use case statement for fixed ROM outputs [OK]

Common Mistakes:

• Assigning to wire arrays
• Initializing ROM inside clocked always block
• Not using combinational logic for ROM output