ROM (Read-Only Memory) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a ROM module with input address and output data.

Verilog

module rom(input [3:0] addr, output reg [7:0] data);
  always @(*) begin
    case([1])
      4'd0: data = 8'hA1;
      4'd1: data = 8'hB2;
      default: data = 8'h00;
    endcase
  end
endmodule

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Adata

Baddr

Cinput

Doutput

Attempts:

3 left

💡 Hint

Common Mistakes

Using the output signal instead of the address in the case statement.

Forgetting to use the input address signal.

The case statement uses the input address addr to select the ROM data.

2fill in blank

medium

Complete the code to initialize the ROM contents using a Verilog array.

Verilog

reg [7:0] rom_mem [0:15];
initial begin
  rom_mem[0] = 8'h1A;
  rom_mem[1] = 8'h2B;
  rom_mem[2] = 8'h3C;
  rom_mem[3] = 8'h4D;
  // ... other initializations
end

always @(*) begin
  data = [1];
end

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Arom_mem[addr]

Brom_mem[data]

Crom_mem[0]

Drom_mem[15]

Attempts:

3 left

💡 Hint

Common Mistakes

Indexing the ROM memory with the output signal instead of the address.

Using a fixed index instead of the variable address.

The output data is assigned from the ROM memory at the given address addr.

3fill in blank

hard

Fix the error in the ROM read logic to correctly assign data asynchronously.

Verilog

always @([1]) begin
  data = rom_mem[addr];
end

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Aposedge clk

Bnegedge clk

Caddr

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edges in sensitivity list for asynchronous ROM read.

Leaving sensitivity list empty or incorrect.

The ROM output should update whenever the address changes, so the sensitivity list must include addr.

4fill in blank

hard

Fill both blanks to create a ROM module with parameterized data width and depth.

Verilog

module rom #(parameter WIDTH = [1], DEPTH = [2]) (
  input [$clog2(DEPTH)-1:0] addr,
  output reg [WIDTH-1:0] data
);
  reg [WIDTH-1:0] mem [0:DEPTH-1];
  always @(*) begin
    data = mem[addr];
  end
endmodule

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A8

B16

C256

D1024

Attempts:

3 left

💡 Hint

Common Mistakes

Using invalid parameter values that don't match the address width.

Mixing up WIDTH and DEPTH values.

The data width is set to 8 bits and the depth to 256 locations, common ROM sizes.

5fill in blank

hard

Fill all three blanks to implement a ROM with synchronous read using a clock.

Verilog

module rom_sync(
  input clk,
  input [3:0] addr,
  output reg [7:0] data
);
  reg [7:0] mem [0:15];
  always @(posedge [1]) begin
    data <= mem[[2]];
  end
endmodule

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Aclk

Baddr

Cdata

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using the wrong signal in the sensitivity list.

Indexing memory with the output data signal.

The synchronous ROM reads data on the rising edge of the clock clk, using the address addr to index memory.