ROM (Read-Only Memory) in Verilog - Mini Project: Build & Apply

ROM (Read-Only Memory) in Verilog

📖 Scenario: You are designing a simple digital system that needs to store fixed data values. This data will not change during operation, so you decide to use a Read-Only Memory (ROM) module in Verilog to hold these values.

🎯 Goal: Build a ROM module in Verilog that stores 8 fixed 4-bit values. You will create the ROM data, set up the address input, implement the ROM logic, and finally output the stored data based on the address.

📋 What You'll Learn

Create a ROM data array with 8 entries, each 4 bits wide, with exact values

Create an address input variable to select which data to output

Implement the ROM logic using a case statement to output data based on the address

Print the output data for a given address

💡 Why This Matters

🌍 Real World

ROM modules are used in digital systems to store fixed data like lookup tables, font data, or configuration constants that do not change during operation.

💼 Career

Understanding ROM design in Verilog is important for hardware engineers working on FPGA or ASIC designs where fixed data storage is required.

1

Create ROM data array

Create a reg [3:0] rom_data [0:7] array and initialize it with these exact values: 4'b1000, 4'b0111, 4'b0110, 4'b0101, 4'b0100, 4'b0011, 4'b0010, 4'b0001.

Verilog

// Your code here to create and initialize rom_data array

Need a hint?

Use a reg array with 8 elements, each 4 bits wide. Initialize with the exact binary values in the order given.

2

Create address input

Create a reg [2:0] address variable to select the ROM data index.

Verilog

reg [3:0] rom_data [0:7] = '{4'b1000, 4'b0111, 4'b0110, 4'b0101, 4'b0100, 4'b0011, 4'b0010, 4'b0001};
// Your code here to create address variable

Need a hint?

The address should be 3 bits wide to select 8 locations (0 to 7).

3

Implement ROM output logic

Create a reg [3:0] data_out and use a case statement inside an always @(*) block to assign data_out the value from rom_data at the given address.

Verilog

reg [3:0] rom_data [0:7] = '{4'b1000, 4'b0111, 4'b0110, 4'b0101, 4'b0100, 4'b0011, 4'b0010, 4'b0001};
reg [2:0] address;
// Your code here to implement ROM output logic

Need a hint?

Use a combinational always block with a case statement to select the output based on address.

4

Display ROM output for a given address

Set address = 3'd3 and use $display to print data_out in binary format.

Verilog

reg [3:0] rom_data [0:7] = '{4'b1000, 4'b0111, 4'b0110, 4'b0101, 4'b0100, 4'b0011, 4'b0010, 4'b0001};
reg [2:0] address;
reg [3:0] data_out;
always @(*) begin
    case(address)
        3'd0: data_out = rom_data[0];
        3'd1: data_out = rom_data[1];
        3'd2: data_out = rom_data[2];
        3'd3: data_out = rom_data[3];
        3'd4: data_out = rom_data[4];
        3'd5: data_out = rom_data[5];
        3'd6: data_out = rom_data[6];
        3'd7: data_out = rom_data[7];
        default: data_out = 4'b0000;
    endcase
end
// Your code here to set address and display data_out

Need a hint?

Set the address to 3 and use $display to print the 4-bit output in binary.