ROM (Read-Only Memory) in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is ROM in Verilog?

ROM stands for Read-Only Memory. It is a memory block where data is stored permanently and cannot be changed during simulation or operation.

beginner

How do you declare a ROM in Verilog?

You declare ROM as a reg array with fixed values assigned at initialization, for example: <br> reg [7:0] rom [0:15]; <br> Then you assign values inside an initial block.

beginner

Why use an initial block for ROM in Verilog?

The initial block sets the fixed data values in ROM at the start of simulation. Since ROM data doesn't change, this block loads the data once.

intermediate

How do you read data from ROM in Verilog?

You use the address input to index the ROM array and output the stored data, usually in a combinational always block or continuous assignment.

beginner

Can ROM contents be changed during simulation?

No, ROM contents are fixed and cannot be changed during simulation or operation. They are read-only.

What does ROM stand for in Verilog?

A Random-Only Memory

B Read-Only Memory

C Read-Operate Memory

D Register-Only Memory

ROM means Read-Only Memory, which stores fixed data.

How do you initialize ROM data in Verilog?

A Using a function

B Using always @(posedge clk)

C Using an initial block

D Using a task

ROM data is set once at the start using an initial block.

Which Verilog data type is commonly used to declare ROM?

A reg array

B real

C integer

D wire

ROM is declared as a reg array to hold multiple data values.

Can ROM contents be modified during simulation?

A No, they are fixed

B Yes, anytime

C Only during reset

D Only with special commands

ROM contents are fixed and cannot be changed during simulation.

How do you access data stored in ROM?

A By writing to the ROM address

B By resetting the ROM

C By enabling the ROM write signal

D By reading from the ROM address

You read data from ROM by providing an address to access stored data.

Explain how to create a simple ROM in Verilog and how to read data from it.

Think about how you store fixed data and then use an address to get that data.

Why is ROM called 'read-only' and what does that mean in Verilog simulation?

Consider what 'read-only' means in everyday life and how it applies here.