Ring counter in Verilog - Step-by-Step Execution

Concept Flow - Ring counter

Start with one bit set to 1

↓

Shift bits left by 1

↓

Wrap the leftmost bit to rightmost

↓

Output current state

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Repeat on clock pulse

A ring counter cycles a single '1' bit through a register by shifting and wrapping it around on each clock pulse.

Execution Sample

Verilog

module ring_counter(clk, reset, q);
  input clk, reset;
  output reg [3:0] q;
  always @(posedge clk or posedge reset) begin
    if(reset) q <= 4'b0001;
    else q <= {q[2:0], q[3]};
  end
endmodule

This Verilog code implements a 4-bit ring counter that shifts a single '1' bit around the register on each clock pulse.

Execution Table

Step	Clock Edge	Reset	q Before	q After	Action
1	posedge	1	xxxx	0001	Reset active: q set to 0001
2	posedge	0	0001	0010	Shift left and wrap: 0001 -> 0010
3	posedge	0	0010	0100	Shift left and wrap: 0010 -> 0100
4	posedge	0	0100	1000	Shift left and wrap: 0100 -> 1000
5	posedge	0	1000	0001	Shift left and wrap: 1000 -> 0001
6	posedge	0	0001	0010	Shift left and wrap: 0001 -> 0010

💡 Execution continues cycling the '1' bit around the 4-bit register on each clock pulse.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
q	xxxx	0001	0010	0100	1000	0001	0010

Key Moments - 3 Insights

Why does the '1' bit move position instead of multiple bits being set?

Because the code shifts the bits left and wraps the leftmost bit to the rightmost position, only one '1' bit moves around, as shown in execution_table rows 2 to 6.

What happens when reset is active?

When reset is 1 (row 1), the register q is set to 0001, starting the ring counter with a single '1' bit at the rightmost position.

Why does the value wrap from 1000 back to 0001?

Because the code concatenates q[2:0] with q[3], moving the leftmost bit to the rightmost position, as seen in row 5.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of q after the clock edge?

A 1000

B 0010

C 0100

D 0001

💡 Hint

Check the 'q After' column in row 3 of the execution_table.

At which step does the reset signal set q to 0001?

A Step 4

B Step 1

C Step 2

D Step 5

💡 Hint

Look at the 'Reset' column and 'Action' in the first row of the execution_table.

If the code did not wrap the leftmost bit to the rightmost, what would happen to q after several clock pulses?

A The '1' bit would disappear (all zeros)

B The '1' bit would stay in place

C Multiple bits would be set to '1'

D The register would hold the initial value forever

💡 Hint

Consider what happens if the leftmost bit is lost instead of wrapped, check the shifting logic in the code.

Concept Snapshot

Ring counter cycles a single '1' bit through a register.
Syntax: q <= {q[2:0], q[3]}; shifts left and wraps bit.
Reset sets q to 0001 to start.
On each clock, '1' moves one position left.
Useful for sequence generation and timing.

Full Transcript

A ring counter in Verilog uses a register where only one bit is set to '1' at a time. On each clock pulse, the bits shift left, and the leftmost bit wraps around to the rightmost position. This creates a repeating pattern where the '1' bit moves around the register. The reset signal initializes the register to 0001, starting the cycle. The code example shows a 4-bit ring counter with this behavior. The execution table traces each clock pulse, showing how the value of q changes step-by-step. Key moments clarify why only one bit moves, what reset does, and how wrapping works. The visual quiz tests understanding of these steps. This concept is useful for timing and sequence control in digital circuits.