Ring counter in Verilog - Deep Dive

Overview - Ring counter

What is it?

A ring counter is a type of digital circuit that cycles a single '1' bit through a series of flip-flops arranged in a loop. It moves this '1' around the ring, one position at a time, with all other bits being '0'. This creates a repeating pattern that can be used to count or sequence events in hardware.

Why it matters

Ring counters simplify the design of sequential circuits by providing a clear, predictable pattern of states with minimal hardware. Without ring counters, designers would need more complex logic to track sequences, making circuits larger and slower. They are essential in timing, control, and state machine applications where precise step-by-step progression is needed.

Where it fits

Before learning ring counters, you should understand basic digital logic, flip-flops, and binary counting. After mastering ring counters, you can explore more complex counters like Johnson counters, state machines, and timing control circuits.

Mental Model

Core Idea

A ring counter is like a single glowing light moving around a circle of bulbs, turning one on at a time in a fixed sequence.

Think of it like...

Imagine a group of friends sitting in a circle passing a single glowing baton. Only one friend holds the glowing baton at a time, and it moves to the next friend each turn, repeating endlessly.

┌─────┐   ┌─────┐   ┌─────┐   ┌─────┐
│ FF1 │→ │ FF2 │→ │ FF3 │→ │ FF4 │
└─────┘   └─────┘   └─────┘   └─────┘
   ↑                             ↓
   └───────────────◄─────────────┘

Only one flip-flop output is '1' at a time, circulating around.

Build-Up - 7 Steps

1

Foundation

Understanding flip-flops basics

Concept: Learn what a flip-flop is and how it stores a single bit of data.

A flip-flop is a basic memory element in digital circuits. It can hold a '0' or '1' until told to change. The most common type is the D flip-flop, which captures the input value on a clock edge and holds it steady until the next clock.

Result

You can store one bit of information reliably and change it only at specific times.

Understanding flip-flops is essential because ring counters use them as building blocks to hold and move bits in sequence.

2

Foundation

Basic binary counters overview

Concept: See how simple counters count up in binary using flip-flops.

Binary counters use flip-flops connected so that each clock pulse increases the binary number stored. For example, a 4-bit binary counter counts from 0000 to 1111 in binary, increasing by one each clock.

Result

You get a sequence of binary numbers representing counts.

Knowing binary counters helps you appreciate how ring counters differ by cycling a single '1' instead of counting in binary.

3

Intermediate

Ring counter structure and operation

Concept: Learn how flip-flops connect in a ring to circulate a single '1'.

In a ring counter, the output of the last flip-flop connects back to the input of the first. Initially, only one flip-flop is set to '1', and the rest are '0'. On each clock pulse, the '1' moves to the next flip-flop, creating a circulating pattern.

Result

The '1' bit moves step-by-step around the ring, repeating the cycle.

This structure creates a simple, predictable sequence with minimal logic, ideal for timing and control.

4

Intermediate

Verilog code for a 4-bit ring counter

🤔Before reading on: do you think the ring counter needs complex logic gates or just flip-flops connected in a loop? Commit to your answer.

Concept: Implement a ring counter in Verilog using flip-flops and a reset to initialize the '1'.

module ring_counter(clk, reset, q); input clk, reset; output reg [3:0] q; always @(posedge clk or posedge reset) begin if (reset) q <= 4'b0001; // Initialize with one '1' else q <= {q[2:0], q[3]}; // Rotate left end endmodule

Result

On each clock, the '1' moves left through the 4 bits: 0001 → 0010 → 0100 → 1000 → 0001 ...

Knowing that a simple shift and wrap-around creates the ring counter helps you write concise, efficient hardware code.

5

Intermediate

Reset and initialization importance

Concept: Understand why setting the initial state is critical for ring counters.

Without a proper reset, the ring counter might start with all zeros or multiple ones, breaking the sequence. The reset sets exactly one flip-flop to '1' to start the cycle correctly.

Result

The ring counter always begins with a valid state and cycles predictably.

Recognizing the need for initialization prevents bugs where the counter never cycles or behaves unpredictably.

6

Advanced

Scaling ring counters and limitations

🤔Before reading on: do you think ring counters scale efficiently to very large sizes? Commit to your answer.

Concept: Explore how ring counters behave as the number of bits grows and their practical limits.

Ring counters require one flip-flop per state, so for N states, you need N flip-flops. This can be inefficient for large counts compared to binary counters. Also, the speed depends on the clock and flip-flop delays.

Result

Ring counters are best for small to medium sequences where simplicity and timing are key, but not for large counts.

Understanding scaling helps you choose the right counter type for your design needs.

7

Expert

Using ring counters in state machines

🤔Before reading on: do you think ring counters can replace complex state machines? Commit to your answer.

Concept: Learn how ring counters can implement simple state machines with minimal logic.

Ring counters naturally cycle through states, making them ideal for simple state machines where each state corresponds to one flip-flop being '1'. This reduces decoding logic and improves timing. However, complex state machines with many transitions need more flexible designs.

Result

You get efficient, fast state sequencing with minimal hardware for simple control tasks.

Knowing this use case shows how ring counters optimize hardware design beyond just counting.

Under the Hood

Internally, each flip-flop holds one bit. On each clock pulse, the output of one flip-flop feeds the input of the next, passing the '1' bit around the ring. The hardware uses edge-triggered flip-flops that update simultaneously, ensuring the '1' moves cleanly without glitches.

Why designed this way?

Ring counters were designed to provide a simple, reliable way to cycle through states with minimal logic. Alternatives like binary counters require decoding logic to identify states, increasing complexity. The ring counter's design trades hardware efficiency for simplicity and speed in small sequences.

┌───────────────┐
│   Flip-Flop 1 │
│   q[0] = 1   │
└───────┬───────┘
        │
        ▼
┌───────────────┐
│   Flip-Flop 2 │
│   q[1] = 0   │
└───────┬───────┘
        │
        ▼
┌───────────────┐
│   Flip-Flop 3 │
│   q[2] = 0   │
└───────┬───────┘
        │
        ▼
┌───────────────┐
│   Flip-Flop 4 │
│   q[3] = 0   │
└───────┬───────┘
        │
        └───────────────┐
                        ▼
                  (Back to Flip-Flop 1)

Myth Busters - 4 Common Misconceptions

Quick: Does a ring counter count in binary like a normal counter? Commit to yes or no.

Common Belief: A ring counter counts in binary numbers just like a regular binary counter.

Reality: A ring counter does not count in binary; it cycles a single '1' through flip-flops, producing a one-hot sequence, not binary numbers.

Why it matters: Confusing ring counters with binary counters leads to wrong expectations and design errors when interpreting output states.

Quick: Can a ring counter start correctly without a reset? Commit to yes or no.

Common Belief: A ring counter will always start cycling correctly even without an explicit reset.

Reality: Without a reset, the ring counter may start with all zeros or multiple ones, causing it to malfunction or get stuck.

Why it matters: Ignoring initialization can cause the circuit to never enter the intended sequence, leading to system failures.

Quick: Is a ring counter efficient for very large counts? Commit to yes or no.

Common Belief: Ring counters are efficient and practical for counting very large numbers.

Reality: Ring counters require one flip-flop per state, making them inefficient and hardware-heavy for large counts compared to binary counters.

Why it matters: Using ring counters for large counts wastes hardware and can slow down the system unnecessarily.

Quick: Can ring counters implement any complex state machine easily? Commit to yes or no.

Common Belief: Ring counters can replace any complex state machine design.

Reality: Ring counters are suitable only for simple, linear state sequences; complex state machines need more flexible designs.

Why it matters: Trying to use ring counters for complex logic leads to rigid, hard-to-maintain designs.

Expert Zone

1

Ring counters produce one-hot outputs, which simplify decoding logic and reduce glitches in timing-sensitive designs.

2

The wrap-around connection in ring counters must be carefully designed to avoid race conditions and ensure stable transitions.

3

In FPGA implementations, ring counters can map efficiently to shift register primitives, saving resources compared to general logic.

When NOT to use

Avoid ring counters when you need to count large numbers or require flexible state transitions. Use binary counters or programmable state machines instead for efficiency and versatility.

Production Patterns

Ring counters are commonly used in hardware sequencers, LED chasers, timing circuits, and simple control state machines where predictable, cyclic behavior is needed with minimal logic.

Connections

One-hot encoding

Ring counters produce one-hot encoded outputs as a natural consequence of their design.

Understanding ring counters deepens comprehension of one-hot encoding, which is widely used in digital design for simplifying state decoding.

Shift registers

Ring counters are a special case of shift registers with feedback to form a loop.

Knowing this connection helps leverage shift register concepts and hardware primitives to implement ring counters efficiently.

Conveyor belt systems (industrial engineering)

Both ring counters and conveyor belts move a single item step-by-step in a looped path.

Recognizing this similarity shows how sequential movement concepts apply across hardware and physical systems, aiding cross-disciplinary problem solving.

Common Pitfalls

#1 Starting ring counter without reset causes invalid states.

Wrong approach:

always @(posedge clk) begin
q <= {q[2:0], q[3]}; // No reset initialization
end

Correct approach:

always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0001;
else
q <= {q[2:0], q[3]};
end

Root cause:

Forgetting to initialize the ring counter leaves it in an unknown or all-zero state, breaking the cycle.

#2 Using ring counter for large counts wastes hardware.

Wrong approach:

// 64-bit ring counter
reg [63:0] q;
// This uses 64 flip-flops for counting 64 states

Correct approach:

// Use binary counter for large counts
reg [5:0] count;
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else count <= count + 1;
end

Root cause:

Misunderstanding ring counters as general counters leads to inefficient designs for large state spaces.

#3 Assuming ring counter outputs are binary numbers.

Wrong approach:

// Interpreting q as binary count
if (q == 4'b0010) // expecting count 2
// But q is one-hot, not binary

Correct approach:

// Decode one-hot outputs properly
if (q[1] == 1'b1) // state 2 active

Root cause:

Confusing one-hot encoding with binary counting causes logic errors in state detection.

Key Takeaways

A ring counter cycles a single '1' bit through flip-flops arranged in a loop, creating a simple repeating sequence.

It requires careful initialization with a reset to start the cycle correctly and avoid invalid states.

Ring counters produce one-hot outputs, simplifying decoding but using more hardware than binary counters for large counts.

They are ideal for small, predictable sequences and simple state machines but not for complex or large counting tasks.

Understanding ring counters connects to broader concepts like shift registers and one-hot encoding, enriching digital design skills.

Practice

1.

What is the main function of a ring counter in Verilog?

easy

A. It generates random numbers for testing.

B. It counts the number of clock pulses in binary.

C. It stores multiple bits of data simultaneously.

D. It circulates a single '1' bit through a register chain.

Solution

1. Step 1: Understand ring counter behavior

   A ring counter moves a single '1' bit around a group of bits in a loop, unlike a binary counter which counts in binary.

2. Step 2: Identify the correct function

   The main function is to circulate one '1' bit through the register chain, which matches It circulates a single '1' bit through a register chain..

3. Final Answer:

   It circulates a single '1' bit through a register chain. -> Option D

4. Quick Check:

   Ring counter = single '1' bit circulation [OK]

Hint: Ring counter moves one '1' bit around registers [OK]

Common Mistakes:

• Confusing ring counter with binary counter
• Thinking it stores multiple bits set to '1'
• Assuming it generates random values

2.

Which of the following is the correct way to declare a 4-bit ring counter register in Verilog?

?

easy

A. reg [3:0] ring_counter; // 4-bit register

B. wire [4:0] ring_counter; // 5-bit wire

C. reg ring_counter[3:0]; // 4 separate registers

D. integer ring_counter; // integer type

Solution

1. Step 1: Understand register declaration syntax

   In Verilog, a 4-bit register is declared as reg [3:0] name; where bits are indexed from 3 down to 0.

2. Step 2: Check each option

   reg [3:0] ring_counter; // 4-bit register correctly declares a 4-bit register. wire [4:0] ring_counter; // 5-bit wire uses wire and 5 bits, which is incorrect. reg ring_counter[3:0]; // 4 separate registers declares an array of 4 registers, not a 4-bit register. integer ring_counter; // integer type declares an integer, not a bit vector.

3. Final Answer:

   reg [3:0] ring_counter; // 4-bit register -> Option A

4. Quick Check:

   4-bit register = reg [3:0] [OK]

Hint: Use reg [3:0] for 4-bit registers in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Confusing array of registers with bit vector
• Using integer for bit-level operations

3.

Consider the following Verilog code snippet for a 4-bit ring counter:

module ring_counter(clk, reset, q);
  input clk, reset;
  output reg [3:0] q;
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[2:0], q[3]};
  end
endmodule

What will be the value of q after 3 clock cycles following a reset?

medium

A. 4'b0100

B. 4'b1000

C. 4'b0010

D. 4'b0001

Solution

1. Step 1: Analyze initial reset value

   On reset, q is set to 4'b0001.

2. Step 2: Trace the bit rotation for 3 clock cycles

   Each clock cycle shifts bits left with wrap-around:
   Cycle 1: q = {q[2:0], q[3]} = {000,1} = 4'b0010
   Cycle 2: q = {010,0} = 4'b0100
   Cycle 3: q = {100,0} = 4'b1000

3. Final Answer:

   4'b1000 -> Option B

4. Quick Check:

   Rotate left 3 times from 0001 = 1000 [OK]

Hint: Rotate bits left each clock cycle after reset [OK]

Common Mistakes:

• Confusing bit order in rotation
• Forgetting wrap-around of MSB to LSB
• Misreading reset initial value

4.

Identify the error in this Verilog ring counter code snippet:

always @(posedge clk) begin
  if (reset)
    q <= 4'b0001;
  else
    q <= {q[3], q[2:0]};
end

medium

A. The register q is not declared as reg.

B. Reset condition should be asynchronous.

C. The concatenation order is incorrect for rotating bits.

D. The clock edge sensitivity list is missing reset.

Solution

1. Step 1: Understand the intended rotation

   The code intends to rotate bits left, but concatenation order is {q[3], q[2:0]}, which places MSB first, then lower bits, effectively no rotation.

2. Step 2: Identify correct rotation syntax

   Correct rotation left should be {q[2:0], q[3]} to move MSB to LSB position.

3. Final Answer:

   The concatenation order is incorrect for rotating bits. -> Option C

4. Quick Check:

   Rotation needs {q[2:0], q[3]} not {q[3], q[2:0]} [OK]

Hint: Check bit order in concatenation for rotation [OK]

Common Mistakes:

• Swapping bit order in concatenation
• Ignoring asynchronous reset requirement
• Forgetting to declare registers properly

5.

You want to design a 5-bit ring counter that starts with 5'b00001 on reset and rotates the '1' bit right on each clock cycle. Which of the following always block implementations correctly achieves this?

?

hard

A. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[0], q[4:1]};
end

B. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[3:0], q[4]};
end

C. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b10000;
else
q <= {q[0], q[4:1]};
end

D. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[1:0], q[4:2]};
end

Solution

1. Step 1: Understand right rotation of bits

   Right rotation moves the least significant bit (LSB) to the most significant bit (MSB) position, shifting others right.

2. Step 2: Check each option's rotation logic

   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[0], q[4:1]}; end uses {q[0], q[4:1]} which places LSB at MSB and shifts others right, correct for right rotation.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[3:0], q[4]}; end rotates left, incorrect.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b10000; else q <= {q[0], q[4:1]}; end resets to 10000, not 00001.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[1:0], q[4:2]}; end mixes bits incorrectly, not a proper rotation.

3. Final Answer:

   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[0], q[4:1]}; end -> Option A

4. Quick Check:

   Right rotate = LSB to MSB, shift others right [OK]

Hint: Right rotate: LSB moves to MSB position [OK]

Common Mistakes:

• Confusing left and right rotation
• Incorrect reset value for starting bit
• Wrong bit slicing in concatenation