Ring counter in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit ring counter after 3 clock cycles

Consider this 4-bit ring counter Verilog code snippet. What is the value of q after 3 positive clock edges?

Verilog

module ring_counter(input clk, input reset, output reg [3:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[2:0], q[3]};
  end
endmodule

A 4'b0100

B 4'b0010

C 4'b1000

D 4'b0001

💡 Hint

Each clock cycle shifts the '1' bit to the left, wrapping around.

The ring counter starts at 0001. After 1 clock: 0010, after 2 clocks: 0100, after 3 clocks: 1000. But note the code shifts left by concatenating {q[2:0], q[3]}, so the '1' moves from bit 0 to bit 1 after 1 clock, bit 2 after 2 clocks, bit 3 after 3 clocks. So after 3 clocks, q = 1000.

🧠 Conceptual

intermediate

Understanding the purpose of a ring counter

What is the main purpose of a ring counter in digital circuits?

A To store multiple bits of data permanently

B To generate a sequence where a single '1' bit circulates through flip-flops

C To perform arithmetic addition on input signals

D To count the number of clock cycles in binary form

💡 Hint

Think about how the '1' bit moves in a ring counter.

A ring counter circulates a single '1' bit through a series of flip-flops, creating a repeating pattern. It is not a binary counter or an arithmetic unit.

🔧 Debug

advanced

Identify the error in this ring counter code

What error will occur when running this Verilog ring counter code?

Verilog

module ring_counter(input clk, input reset, output reg [3:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[3:1], q[0]};
  end
endmodule

A The '1' bit will not circulate correctly; it will stay in the same position

B No error; the code works as intended

C The counter will count in binary instead of circulating a single '1'

D Syntax error due to incorrect concatenation syntax

💡 Hint

Check how bits are shifted in the concatenation.

The concatenation {q[3:1], q[0]} shifts bits right but keeps the '1' bit in the same position, so the '1' does not circulate properly. The correct shift for a ring counter is to rotate bits left or right properly.

📝 Syntax

advanced

Which option correctly implements a 3-bit ring counter reset?

Which code snippet correctly resets a 3-bit ring counter to 3'b001 on reset?

A if (reset) q <= 3'b001;

B if (reset) q = 3'b001;

C if reset q <= 3'b001;

D if (reset) q <= 3'b1;

💡 Hint

Remember the correct syntax for if statements and non-blocking assignments in always blocks.

Option A uses correct syntax: parentheses around condition and non-blocking assignment <=. Option A uses blocking assignment which is discouraged in sequential logic. Option A misses parentheses. Option A uses wrong bit width literal.

🚀 Application

expert

Number of states in a 5-bit ring counter

How many unique states does a 5-bit ring counter have before repeating the sequence?

A 1

B 10

C 32

D 5

💡 Hint

Think about how the single '1' bit moves through the 5 flip-flops.

A 5-bit ring counter has exactly 5 unique states, each with the '1' bit in a different flip-flop position. After 5 shifts, the pattern repeats.