Ring counter in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit ring counter after 3 clock cycles

Consider this 4-bit ring counter Verilog code snippet. What is the value of q after 3 positive clock edges?

Verilog

module ring_counter(input clk, input reset, output reg [3:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[2:0], q[3]};
  end
endmodule

A 4'b0100

B 4'b0010

C 4'b1000

D 4'b0001

💡 Hint

Each clock cycle shifts the '1' bit to the left, wrapping around.

The ring counter starts at 0001. After 1 clock: 0010, after 2 clocks: 0100, after 3 clocks: 1000. But note the code shifts left by concatenating {q[2:0], q[3]}, so the '1' moves from bit 0 to bit 1 after 1 clock, bit 2 after 2 clocks, bit 3 after 3 clocks. So after 3 clocks, q = 1000.

🧠 Conceptual

intermediate

Understanding the purpose of a ring counter

What is the main purpose of a ring counter in digital circuits?

A To store multiple bits of data permanently

B To generate a sequence where a single '1' bit circulates through flip-flops

C To perform arithmetic addition on input signals

D To count the number of clock cycles in binary form

💡 Hint

Think about how the '1' bit moves in a ring counter.

A ring counter circulates a single '1' bit through a series of flip-flops, creating a repeating pattern. It is not a binary counter or an arithmetic unit.

🔧 Debug

advanced

Identify the error in this ring counter code

What error will occur when running this Verilog ring counter code?

Verilog

module ring_counter(input clk, input reset, output reg [3:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[3:1], q[0]};
  end
endmodule

A The '1' bit will not circulate correctly; it will stay in the same position

B No error; the code works as intended

C The counter will count in binary instead of circulating a single '1'

D Syntax error due to incorrect concatenation syntax

💡 Hint

Check how bits are shifted in the concatenation.

The concatenation {q[3:1], q[0]} shifts bits right but keeps the '1' bit in the same position, so the '1' does not circulate properly. The correct shift for a ring counter is to rotate bits left or right properly.

📝 Syntax

advanced

Which option correctly implements a 3-bit ring counter reset?

Which code snippet correctly resets a 3-bit ring counter to 3'b001 on reset?

A if (reset) q <= 3'b001;

B if (reset) q = 3'b001;

C if reset q <= 3'b001;

D if (reset) q <= 3'b1;

💡 Hint

Remember the correct syntax for if statements and non-blocking assignments in always blocks.

Option A uses correct syntax: parentheses around condition and non-blocking assignment <=. Option A uses blocking assignment which is discouraged in sequential logic. Option A misses parentheses. Option A uses wrong bit width literal.

🚀 Application

expert

Number of states in a 5-bit ring counter

How many unique states does a 5-bit ring counter have before repeating the sequence?

A 1

B 10

C 32

D 5

💡 Hint

Think about how the single '1' bit moves through the 5 flip-flops.

A 5-bit ring counter has exactly 5 unique states, each with the '1' bit in a different flip-flop position. After 5 shifts, the pattern repeats.

Practice

1.

What is the main function of a ring counter in Verilog?

easy

A. It generates random numbers for testing.

B. It counts the number of clock pulses in binary.

C. It stores multiple bits of data simultaneously.

D. It circulates a single '1' bit through a register chain.

Solution

1. Step 1: Understand ring counter behavior

   A ring counter moves a single '1' bit around a group of bits in a loop, unlike a binary counter which counts in binary.

2. Step 2: Identify the correct function

   The main function is to circulate one '1' bit through the register chain, which matches It circulates a single '1' bit through a register chain..

3. Final Answer:

   It circulates a single '1' bit through a register chain. -> Option D

4. Quick Check:

   Ring counter = single '1' bit circulation [OK]

Hint: Ring counter moves one '1' bit around registers [OK]

Common Mistakes:

• Confusing ring counter with binary counter
• Thinking it stores multiple bits set to '1'
• Assuming it generates random values

2.

Which of the following is the correct way to declare a 4-bit ring counter register in Verilog?

?

easy

A. reg [3:0] ring_counter; // 4-bit register

B. wire [4:0] ring_counter; // 5-bit wire

C. reg ring_counter[3:0]; // 4 separate registers

D. integer ring_counter; // integer type

Solution

1. Step 1: Understand register declaration syntax

   In Verilog, a 4-bit register is declared as reg [3:0] name; where bits are indexed from 3 down to 0.

2. Step 2: Check each option

   reg [3:0] ring_counter; // 4-bit register correctly declares a 4-bit register. wire [4:0] ring_counter; // 5-bit wire uses wire and 5 bits, which is incorrect. reg ring_counter[3:0]; // 4 separate registers declares an array of 4 registers, not a 4-bit register. integer ring_counter; // integer type declares an integer, not a bit vector.

3. Final Answer:

   reg [3:0] ring_counter; // 4-bit register -> Option A

4. Quick Check:

   4-bit register = reg [3:0] [OK]

Hint: Use reg [3:0] for 4-bit registers in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Confusing array of registers with bit vector
• Using integer for bit-level operations

3.

Consider the following Verilog code snippet for a 4-bit ring counter:

module ring_counter(clk, reset, q);
  input clk, reset;
  output reg [3:0] q;
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[2:0], q[3]};
  end
endmodule

What will be the value of q after 3 clock cycles following a reset?

medium

A. 4'b0100

B. 4'b1000

C. 4'b0010

D. 4'b0001

Solution

1. Step 1: Analyze initial reset value

   On reset, q is set to 4'b0001.

2. Step 2: Trace the bit rotation for 3 clock cycles

   Each clock cycle shifts bits left with wrap-around:
   Cycle 1: q = {q[2:0], q[3]} = {000,1} = 4'b0010
   Cycle 2: q = {010,0} = 4'b0100
   Cycle 3: q = {100,0} = 4'b1000

3. Final Answer:

   4'b1000 -> Option B

4. Quick Check:

   Rotate left 3 times from 0001 = 1000 [OK]

Hint: Rotate bits left each clock cycle after reset [OK]

Common Mistakes:

• Confusing bit order in rotation
• Forgetting wrap-around of MSB to LSB
• Misreading reset initial value

4.

Identify the error in this Verilog ring counter code snippet:

always @(posedge clk) begin
  if (reset)
    q <= 4'b0001;
  else
    q <= {q[3], q[2:0]};
end

medium

A. The register q is not declared as reg.

B. Reset condition should be asynchronous.

C. The concatenation order is incorrect for rotating bits.

D. The clock edge sensitivity list is missing reset.

Solution

1. Step 1: Understand the intended rotation

   The code intends to rotate bits left, but concatenation order is {q[3], q[2:0]}, which places MSB first, then lower bits, effectively no rotation.

2. Step 2: Identify correct rotation syntax

   Correct rotation left should be {q[2:0], q[3]} to move MSB to LSB position.

3. Final Answer:

   The concatenation order is incorrect for rotating bits. -> Option C

4. Quick Check:

   Rotation needs {q[2:0], q[3]} not {q[3], q[2:0]} [OK]

Hint: Check bit order in concatenation for rotation [OK]

Common Mistakes:

• Swapping bit order in concatenation
• Ignoring asynchronous reset requirement
• Forgetting to declare registers properly

5.

You want to design a 5-bit ring counter that starts with 5'b00001 on reset and rotates the '1' bit right on each clock cycle. Which of the following always block implementations correctly achieves this?

?

hard

A. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[0], q[4:1]};
end

B. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[3:0], q[4]};
end

C. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b10000;
else
q <= {q[0], q[4:1]};
end

D. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[1:0], q[4:2]};
end

Solution

1. Step 1: Understand right rotation of bits

   Right rotation moves the least significant bit (LSB) to the most significant bit (MSB) position, shifting others right.

2. Step 2: Check each option's rotation logic

   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[0], q[4:1]}; end uses {q[0], q[4:1]} which places LSB at MSB and shifts others right, correct for right rotation.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[3:0], q[4]}; end rotates left, incorrect.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b10000; else q <= {q[0], q[4:1]}; end resets to 10000, not 00001.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[1:0], q[4:2]}; end mixes bits incorrectly, not a proper rotation.

3. Final Answer:

   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[0], q[4:1]}; end -> Option A

4. Quick Check:

   Right rotate = LSB to MSB, shift others right [OK]

Hint: Right rotate: LSB moves to MSB position [OK]

Common Mistakes:

• Confusing left and right rotation
• Incorrect reset value for starting bit
• Wrong bit slicing in concatenation