Ring counter in Verilog - Mini Project: Build & Apply

Ring counter

📖 Scenario: You are designing a simple digital circuit called a ring counter. It is used in electronics to cycle through a sequence of states, one at a time, in a repeating loop.Imagine a circle of lights where only one light is on at a time, and the light moves to the next position every clock pulse.

🎯 Goal: Build a 4-bit ring counter in Verilog that cycles a single '1' bit through four flip-flops on each clock pulse.

📋 What You'll Learn

Create a 4-bit register called ring_reg initialized with the value 4'b0001

Create a clock input called clk

On each rising edge of clk, shift the '1' bit to the left, wrapping around to the rightmost bit

Output the current state of the ring counter on a 4-bit output called ring_out

💡 Why This Matters

🌍 Real World

Ring counters are used in digital electronics for sequencing tasks, timing circuits, and controlling devices in a fixed order.

💼 Career

Understanding ring counters helps in designing state machines and control logic in hardware design jobs such as FPGA or ASIC development.

1

DATA SETUP: Create the 4-bit register

Create a 4-bit register called ring_reg and initialize it with the value 4'b0001 inside a Verilog module named ring_counter. Also declare inputs and outputs as needed.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
// Your code here
endmodule

Need a hint?

Start by declaring the module with input clk and output reg [3:0] ring_out. Then create a register ring_reg initialized to 4'b0001.

2

CONFIGURATION: Assign output from the register

Inside the ring_counter module, assign the output ring_out to always equal the current value of ring_reg.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
    reg [3:0] ring_reg = 4'b0001;
    // Your code here
endmodule

Need a hint?

Use an always @(*) block to continuously assign ring_out the value of ring_reg.

3

CORE LOGIC: Shift the register on clock rising edge

Add an always @(posedge clk) block inside the ring_counter module. Inside it, update ring_reg by shifting its bits left by one position. The leftmost bit should wrap around to the rightmost bit to create the ring effect.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
    reg [3:0] ring_reg = 4'b0001;
    
    always @(*) begin
        ring_out = ring_reg;
    end
    // Your code here
endmodule

Need a hint?

Use concatenation to shift left and wrap the leftmost bit to the rightmost position.

4

OUTPUT: Test the ring counter output

Write a testbench module named testbench that instantiates ring_counter. Generate a clock signal that toggles every 5 time units. Run the simulation for 40 time units and print the value of ring_out at each positive clock edge using $display.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
    reg [3:0] ring_reg = 4'b0001;
    
    always @(*) begin
        ring_out = ring_reg;
    end

    always @(posedge clk) begin
        ring_reg <= {ring_reg[2:0], ring_reg[3]};
    end
endmodule

// Your code here

Need a hint?

Create a testbench that toggles clk every 5 time units. Use $display inside an initial block to print ring_out at each rising clock edge.