Ring counter in Verilog - Mini Project: Build & Apply

Ring counter

📖 Scenario: You are designing a simple digital circuit called a ring counter. It is used in electronics to cycle through a sequence of states, one at a time, in a repeating loop.Imagine a circle of lights where only one light is on at a time, and the light moves to the next position every clock pulse.

🎯 Goal: Build a 4-bit ring counter in Verilog that cycles a single '1' bit through four flip-flops on each clock pulse.

📋 What You'll Learn

Create a 4-bit register called ring_reg initialized with the value 4'b0001

Create a clock input called clk

On each rising edge of clk, shift the '1' bit to the left, wrapping around to the rightmost bit

Output the current state of the ring counter on a 4-bit output called ring_out

💡 Why This Matters

🌍 Real World

Ring counters are used in digital electronics for sequencing tasks, timing circuits, and controlling devices in a fixed order.

💼 Career

Understanding ring counters helps in designing state machines and control logic in hardware design jobs such as FPGA or ASIC development.

1

DATA SETUP: Create the 4-bit register

Create a 4-bit register called ring_reg and initialize it with the value 4'b0001 inside a Verilog module named ring_counter. Also declare inputs and outputs as needed.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
// Your code here
endmodule

Hint

Start by declaring the module with input clk and output reg [3:0] ring_out. Then create a register ring_reg initialized to 4'b0001.

2

CONFIGURATION: Assign output from the register

Inside the ring_counter module, assign the output ring_out to always equal the current value of ring_reg.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
    reg [3:0] ring_reg = 4'b0001;
    // Your code here
endmodule

Hint

Use an always @(*) block to continuously assign ring_out the value of ring_reg.

3

CORE LOGIC: Shift the register on clock rising edge

Add an always @(posedge clk) block inside the ring_counter module. Inside it, update ring_reg by shifting its bits left by one position. The leftmost bit should wrap around to the rightmost bit to create the ring effect.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
    reg [3:0] ring_reg = 4'b0001;
    
    always @(*) begin
        ring_out = ring_reg;
    end
    // Your code here
endmodule

Hint

Use concatenation to shift left and wrap the leftmost bit to the rightmost position.

4

OUTPUT: Test the ring counter output

Write a testbench module named testbench that instantiates ring_counter. Generate a clock signal that toggles every 5 time units. Run the simulation for 40 time units and print the value of ring_out at each positive clock edge using $display.

Verilog

module ring_counter(input clk, output reg [3:0] ring_out);
    reg [3:0] ring_reg = 4'b0001;
    
    always @(*) begin
        ring_out = ring_reg;
    end

    always @(posedge clk) begin
        ring_reg <= {ring_reg[2:0], ring_reg[3]};
    end
endmodule

// Your code here

Hint

Create a testbench that toggles clk every 5 time units. Use $display inside an initial block to print ring_out at each rising clock edge.

Practice

1.

What is the main function of a ring counter in Verilog?

easy

A. It generates random numbers for testing.

B. It counts the number of clock pulses in binary.

C. It stores multiple bits of data simultaneously.

D. It circulates a single '1' bit through a register chain.

Solution

1. Step 1: Understand ring counter behavior

   A ring counter moves a single '1' bit around a group of bits in a loop, unlike a binary counter which counts in binary.

2. Step 2: Identify the correct function

   The main function is to circulate one '1' bit through the register chain, which matches It circulates a single '1' bit through a register chain..

3. Final Answer:

   It circulates a single '1' bit through a register chain. -> Option D

4. Quick Check:

   Ring counter = single '1' bit circulation [OK]

Hint: Ring counter moves one '1' bit around registers [OK]

Common Mistakes:

• Confusing ring counter with binary counter
• Thinking it stores multiple bits set to '1'
• Assuming it generates random values

2.

Which of the following is the correct way to declare a 4-bit ring counter register in Verilog?

?

easy

A. reg [3:0] ring_counter; // 4-bit register

B. wire [4:0] ring_counter; // 5-bit wire

C. reg ring_counter[3:0]; // 4 separate registers

D. integer ring_counter; // integer type

Solution

1. Step 1: Understand register declaration syntax

   In Verilog, a 4-bit register is declared as reg [3:0] name; where bits are indexed from 3 down to 0.

2. Step 2: Check each option

   reg [3:0] ring_counter; // 4-bit register correctly declares a 4-bit register. wire [4:0] ring_counter; // 5-bit wire uses wire and 5 bits, which is incorrect. reg ring_counter[3:0]; // 4 separate registers declares an array of 4 registers, not a 4-bit register. integer ring_counter; // integer type declares an integer, not a bit vector.

3. Final Answer:

   reg [3:0] ring_counter; // 4-bit register -> Option A

4. Quick Check:

   4-bit register = reg [3:0] [OK]

Hint: Use reg [3:0] for 4-bit registers in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Confusing array of registers with bit vector
• Using integer for bit-level operations

3.

Consider the following Verilog code snippet for a 4-bit ring counter:

module ring_counter(clk, reset, q);
  input clk, reset;
  output reg [3:0] q;
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 4'b0001;
    else
      q <= {q[2:0], q[3]};
  end
endmodule

What will be the value of q after 3 clock cycles following a reset?

medium

A. 4'b0100

B. 4'b1000

C. 4'b0010

D. 4'b0001

Solution

1. Step 1: Analyze initial reset value

   On reset, q is set to 4'b0001.

2. Step 2: Trace the bit rotation for 3 clock cycles

   Each clock cycle shifts bits left with wrap-around:
   Cycle 1: q = {q[2:0], q[3]} = {000,1} = 4'b0010
   Cycle 2: q = {010,0} = 4'b0100
   Cycle 3: q = {100,0} = 4'b1000

3. Final Answer:

   4'b1000 -> Option B

4. Quick Check:

   Rotate left 3 times from 0001 = 1000 [OK]

Hint: Rotate bits left each clock cycle after reset [OK]

Common Mistakes:

• Confusing bit order in rotation
• Forgetting wrap-around of MSB to LSB
• Misreading reset initial value

4.

Identify the error in this Verilog ring counter code snippet:

always @(posedge clk) begin
  if (reset)
    q <= 4'b0001;
  else
    q <= {q[3], q[2:0]};
end

medium

A. The register q is not declared as reg.

B. Reset condition should be asynchronous.

C. The concatenation order is incorrect for rotating bits.

D. The clock edge sensitivity list is missing reset.

Solution

1. Step 1: Understand the intended rotation

   The code intends to rotate bits left, but concatenation order is {q[3], q[2:0]}, which places MSB first, then lower bits, effectively no rotation.

2. Step 2: Identify correct rotation syntax

   Correct rotation left should be {q[2:0], q[3]} to move MSB to LSB position.

3. Final Answer:

   The concatenation order is incorrect for rotating bits. -> Option C

4. Quick Check:

   Rotation needs {q[2:0], q[3]} not {q[3], q[2:0]} [OK]

Hint: Check bit order in concatenation for rotation [OK]

Common Mistakes:

• Swapping bit order in concatenation
• Ignoring asynchronous reset requirement
• Forgetting to declare registers properly

5.

You want to design a 5-bit ring counter that starts with 5'b00001 on reset and rotates the '1' bit right on each clock cycle. Which of the following always block implementations correctly achieves this?

?

hard

A. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[0], q[4:1]};
end

B. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[3:0], q[4]};
end

C. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b10000;
else
q <= {q[0], q[4:1]};
end

D. always @(posedge clk or posedge reset) begin
if (reset)
q <= 5'b00001;
else
q <= {q[1:0], q[4:2]};
end

Solution

1. Step 1: Understand right rotation of bits

   Right rotation moves the least significant bit (LSB) to the most significant bit (MSB) position, shifting others right.

2. Step 2: Check each option's rotation logic

   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[0], q[4:1]}; end uses {q[0], q[4:1]} which places LSB at MSB and shifts others right, correct for right rotation.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[3:0], q[4]}; end rotates left, incorrect.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b10000; else q <= {q[0], q[4:1]}; end resets to 10000, not 00001.
   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[1:0], q[4:2]}; end mixes bits incorrectly, not a proper rotation.

3. Final Answer:

   always @(posedge clk or posedge reset) begin if (reset) q <= 5'b00001; else q <= {q[0], q[4:1]}; end -> Option A

4. Quick Check:

   Right rotate = LSB to MSB, shift others right [OK]

Hint: Right rotate: LSB moves to MSB position [OK]

Common Mistakes:

• Confusing left and right rotation
• Incorrect reset value for starting bit
• Wrong bit slicing in concatenation