Ring counter in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register named 'ring'.

Verilog

reg [3:0] [1] ;

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Atemp

Bcount

Cdata

Dring

Attempts:

3 left

💡 Hint

Common Mistakes

Using a different variable name like 'count' or 'data'.

The register that holds the ring counter bits is named 'ring'.

2fill in blank

medium

Complete the code to initialize the ring counter with the value 4'b0001.

Verilog

initial begin
  ring = [1] ;
end

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A4'b1000

B4'b0001

C4'b1111

D4'b0010

Attempts:

3 left

💡 Hint

Common Mistakes

Initializing with multiple bits set or wrong bit order.

The ring counter starts with only the least significant bit set to 1, which is 4'b0001.

3fill in blank

hard

Fix the error in the always block to shift the ring counter correctly on each clock cycle.

Verilog

always @(posedge clk) begin
  ring <= {ring[2:0], [1];
end

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Aring[1]

Bring[3]

Cring[0]

D1'b0

Attempts:

3 left

💡 Hint

Common Mistakes

Using ring[3] or 1'b0 breaks the ring behavior.

The ring counter shifts left and the bit shifted in is the previous least significant bit, which is ring[0] to create the ring effect.

4fill in blank

hard

Fill both blanks to complete the module header and port declaration for the ring counter.

Verilog

module ring_counter([1], [2]);
  input clk;
  output reg [3:0] ring;
endmodule

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Aclk

Breset

Cring

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset' or 'enable' in the header when not declared.

The module has inputs and outputs declared in the header: 'clk' as input and 'ring' as output.

5fill in blank

hard

Fill all three blanks to complete the always block with reset logic and ring counter update.

Verilog

always @(posedge clk or posedge [1]) begin
  if ([2]) begin
    ring <= [3];
  end else begin
    ring <= {ring[2:0], ring[0]};
  end
end

Drag options to blanks, or click blank then click option'

Areset

Benable

C4'b0001

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'enable' instead of 'reset' or wrong reset value.

The always block triggers on clock or reset. If reset is high, ring is set to 4'b0001, else it shifts.