Moore machine vs Mealy machine in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a Moore machine output register.

Verilog

reg [1]; // output register for Moore machine

Drag options to blanks, or click blank then click option'

Ay

Boutput

Cstate

Dinput

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'input' or 'state' as output register name.

In a Moore machine, outputs are stored in registers like y that depend only on the state.

2fill in blank

medium

Complete the code to assign output in a Mealy machine based on input.

Verilog

assign y = [1] & x; // Mealy output depends on input x

Drag options to blanks, or click blank then click option'

Anext_state

Bstate

Coutput

Dinput

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'next_state' instead of 'state'.

In a Mealy machine, output depends on the current state and input. Here, state is used with input x.

3fill in blank

hard

Fix the error in the Moore machine state update block.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    state <= [1];
  else
    state <= next_state;
end

Drag options to blanks, or click blank then click option'

A1'b0

Bnext_state

C1'b1

Dstate

Attempts:

3 left

💡 Hint

Common Mistakes

Setting state to '1'b1' or 'next_state' on reset.

On reset, the state should be set to a known initial value, usually 1'b0.

4fill in blank

hard

Fill both blanks to complete the Mealy machine output logic.

Verilog

always @(*) begin
  case(state)
    S0: y = [1] & x;
    S1: y = [2] | x;
    default: y = 0;
  endcase
end

Drag options to blanks, or click blank then click option'

A1'b1

B1'b0

Cstate

Dnext_state

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'state' or 'next_state' as output values.

In Mealy output logic, outputs depend on state and input. Here, 1'b1 and 1'b0 are used as constants for output logic.

5fill in blank

hard

Fill all three blanks to complete the Moore machine output logic.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset) begin
    state <= [1];
    y <= [2];
  end else begin
    state <= next_state;
    y <= [3];
  end
end

Drag options to blanks, or click blank then click option'

A1'b0

B1'b1

Cstate

Dnext_state

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning output from state instead of next_state.

On reset, state and output y are initialized to 1'b0 and 1'b1 respectively. During normal operation, y depends on next_state in a Moore machine.

Practice

1. Which statement correctly describes the output behavior of a Moore machine compared to a Mealy machine?

easy

A. Moore machine output depends only on the current state, while Mealy machine output depends on state and input.

B. Moore machine output depends on input only, Mealy machine output depends on current state only.

C. Both Moore and Mealy machines output depend only on the current input.

D. Moore machine output changes immediately with input, Mealy output changes only on clock edges.

Solution

1. Step 1: Understand Moore machine output dependency

   Moore machine outputs depend solely on the current state, not directly on inputs.

2. Step 2: Understand Mealy machine output dependency

   Mealy machine outputs depend on both the current state and the current input, allowing immediate output changes.

3. Final Answer:

   Moore machine output depends only on the current state, while Mealy machine output depends on state and input. -> Option A

4. Quick Check:

   Moore = state-only output, Mealy = state + input output [OK]

Hint: Moore = state only; Mealy = state plus input [OK]

Common Mistakes:

• Confusing output dependency on input for Moore machine
• Thinking Mealy output changes only on clock edges
• Assuming both machines output depend only on input

2. Which Verilog code snippet correctly models a Moore machine output?

easy

A. always @(input or state) output = input & state;

B. always @(posedge clk) output <= state;

C. always @(posedge clk or input) output <= input;

D. always @(input) output = state;

Solution

1. Step 1: Identify Moore machine output timing

   Moore machine outputs update only on clock edges, so output assignment must be inside a posedge clk block.

2. Step 2: Check code snippets for correct output assignment

   always @(posedge clk) output <= state; uses 'always @(posedge clk)' and assigns output from state, matching Moore behavior.

3. Final Answer:

   always @(posedge clk) output <= state; -> Option B

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output inside posedge clk block [OK]

Common Mistakes:

• Using input sensitivity in Moore output block
• Assigning output directly from input in Moore machine
• Using combinational always block for Moore output

3. Given the following Verilog snippet for a Mealy machine output, what is the output when state = 1 and input = 0?

always @(state or input) begin
  if (state == 1)
    output = input;
  else
    output = 1;
end

medium

A. 1

B. Undefined

C. 0

D. Z (high impedance)

Solution

1. Step 1: Analyze condition when state = 1

   The if condition 'state == 1' is true, so output = input.

2. Step 2: Substitute input value

   Input is 0, so output = 0.

3. Final Answer:

   0 -> Option C

4. Quick Check:

   Mealy output depends on state and input, output = 0 [OK]

Hint: Check state condition first, then assign output [OK]

Common Mistakes:

• Ignoring input value when state is 1
• Assuming output is always 1
• Confusing Mealy output with Moore output

4. Identify the error in this Verilog code snippet intended to model a Moore machine output:

always @(input or state) begin
  output = state;
end

medium

A. Output assignment should use non-blocking '<=' operator.

B. Output should depend on input, not state.

C. The sensitivity list should include only input, not state.

D. Output should be assigned only on clock edge, not on input or state changes.

Solution

1. Step 1: Recall Moore machine output timing

   Moore machine outputs update only on clock edges, not on input or state changes directly.

2. Step 2: Check sensitivity list and assignment timing

   The sensitivity list includes input and state, causing output to update asynchronously, which is incorrect for Moore.

3. Final Answer:

   Output should be assigned only on clock edge, not on input or state changes. -> Option D

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output must update only on clock edge [OK]

Common Mistakes:

• Using combinational always block for Moore output
• Ignoring clock in sensitivity list
• Confusing blocking and non-blocking assignments

5. You want to design a state machine in Verilog where the output must change immediately when the input changes, but also depend on the current state. Which machine type should you choose and why?

hard

A. Mealy machine, because output depends on state and input and can change immediately.

B. Moore machine, because it is simpler to implement and faster to respond.

C. Moore machine, because output depends only on state and changes on clock edges.

D. Neither, because outputs cannot depend on inputs in state machines.

Solution

1. Step 1: Understand output timing requirements

   The output must change immediately when input changes, so it cannot wait for clock edges.

2. Step 2: Match machine type to output behavior

   Mealy machine outputs depend on both state and input and can change immediately with input changes, fitting the requirement.

3. Final Answer:

   Mealy machine, because output depends on state and input and can change immediately. -> Option A

4. Quick Check:

   Immediate output change with input = Mealy machine [OK]

Hint: Immediate output change with input means Mealy machine [OK]

Common Mistakes:

• Choosing Moore machine for immediate output change
• Thinking Moore machine outputs depend on input
• Believing outputs cannot depend on inputs in state machines