Moore machine vs Mealy machine in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a Moore machine output register.

Verilog

reg [1]; // output register for Moore machine

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Ay

Boutput

Cstate

Dinput

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'input' or 'state' as output register name.

In a Moore machine, outputs are stored in registers like y that depend only on the state.

2fill in blank

medium

Complete the code to assign output in a Mealy machine based on input.

Verilog

assign y = [1] & x; // Mealy output depends on input x

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Anext_state

Bstate

Coutput

Dinput

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'next_state' instead of 'state'.

In a Mealy machine, output depends on the current state and input. Here, state is used with input x.

3fill in blank

hard

Fix the error in the Moore machine state update block.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    state <= [1];
  else
    state <= next_state;
end

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A1'b0

Bnext_state

C1'b1

Dstate

Attempts:

3 left

💡 Hint

Common Mistakes

Setting state to '1'b1' or 'next_state' on reset.

On reset, the state should be set to a known initial value, usually 1'b0.

4fill in blank

hard

Fill both blanks to complete the Mealy machine output logic.

Verilog

always @(*) begin
  case(state)
    S0: y = [1] & x;
    S1: y = [2] | x;
    default: y = 0;
  endcase
end

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A1'b1

B1'b0

Cstate

Dnext_state

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'state' or 'next_state' as output values.

In Mealy output logic, outputs depend on state and input. Here, 1'b1 and 1'b0 are used as constants for output logic.

5fill in blank

hard

Fill all three blanks to complete the Moore machine output logic.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset) begin
    state <= [1];
    y <= [2];
  end else begin
    state <= next_state;
    y <= [3];
  end
end

Drag options to blanks, or click blank then click option'

A1'b0

B1'b1

Cstate

Dnext_state

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning output from state instead of next_state.

On reset, state and output y are initialized to 1'b0 and 1'b1 respectively. During normal operation, y depends on next_state in a Moore machine.