Moore machine vs Mealy machine in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output behavior of a Moore machine

Consider this Verilog code snippet of a Moore machine. What is the output y when the input x changes from 0 to 1?

Verilog

module moore_example(input clk, input x, output reg y);
  reg state;
  always @(posedge clk) begin
    case(state)
      0: if (x) state <= 1;
      1: if (!x) state <= 0;
    endcase
  end
  always @(state) begin
    case(state)
      0: y = 0;
      1: y = 1;
    endcase
  end
endmodule

A Output y changes immediately when x changes at clock edge.

B Output y never changes regardless of input x.

C Output y changes only after the clock edge following the input change.

D Output y changes asynchronously with input x.

💡 Hint

Remember that in a Moore machine, outputs depend only on the current state, not directly on inputs.

In a Moore machine, outputs depend solely on the current state. The state updates on the clock edge based on input x. Therefore, output y changes only after the state updates at the clock edge, not immediately when x changes.

❓ Predict Output

intermediate

Output behavior of a Mealy machine

Given this Verilog code snippet of a Mealy machine, what is the output y when input x changes from 0 to 1?

Verilog

module mealy_example(input clk, input x, output reg y);
  reg state;
  always @(posedge clk) begin
    case(state)
      0: if (x) state <= 1;
      1: if (!x) state <= 0;
    endcase
  end
  always @(*) begin
    case(state)
      0: y = x;
      1: y = ~x;
    endcase
  end
endmodule

A Output y changes only when state changes.

B Output y changes immediately when input x changes.

C Output y changes only after the clock edge following the input change.

D Output y never changes regardless of input x.

💡 Hint

In a Mealy machine, outputs depend on both state and inputs.

In a Mealy machine, outputs depend on the current state and the current inputs. Since output y is assigned in a combinational block sensitive to inputs, it changes immediately when input x changes.

🧠 Conceptual

advanced

Difference in output timing between Moore and Mealy machines

Which statement correctly describes the difference in output timing between Moore and Mealy machines?

A Moore machine outputs change only on clock edges; Mealy machine outputs can change asynchronously with inputs.

B Moore machine outputs change asynchronously with inputs; Mealy machine outputs change only on clock edges.

C Both Moore and Mealy machine outputs change only on clock edges.

D Both Moore and Mealy machine outputs change asynchronously with inputs.

💡 Hint

Think about when outputs are updated in each machine type.

Moore machine outputs depend only on the state, which updates on clock edges, so outputs change only at clock edges. Mealy machine outputs depend on state and inputs, so outputs can change immediately when inputs change.

🔧 Debug

advanced

Identify the error in this Mealy machine Verilog code

This Verilog code is intended to implement a Mealy machine. What error will it cause?

Verilog

module mealy_bug(input clk, input x, output reg y);
  reg state;
  always @(posedge clk) begin
    case(state)
      0: if (x) state <= 1;
      1: if (!x) state <= 0;
    endcase
  end
  always @(state) begin
    case(state)
      0: y = x;
      1: y = ~x;
    endcase
  end
endmodule

A No error; code works as intended.

B Output y does not update immediately when input x changes.

C Syntax error due to missing initial state assignment.

D Output y is not updated correctly because it depends on input x but is only sensitive to state.

💡 Hint

Check the sensitivity list of the output logic block.

The output y depends on input x but the always block is sensitive only to state changes. This means y will not update immediately when x changes, causing incorrect behavior for a Mealy machine.

🚀 Application

expert

Design choice for output stability in FSM

You need to design a finite state machine in Verilog where output glitches must be avoided and outputs should be stable during the clock cycle. Which machine type is best suited and why?

A Moore machine, because outputs depend only on state and change synchronously with clock edges.

B Mealy machine, because outputs depend on inputs and can change immediately, reducing latency.

C Mealy machine, because outputs are stable during the clock cycle.

D Moore machine, because outputs change asynchronously with inputs.

💡 Hint

Consider output stability and timing in your choice.

Moore machines produce outputs based only on the current state, which changes synchronously on clock edges. This ensures outputs are stable and free from glitches during the clock cycle, making Moore machines suitable for designs requiring stable outputs.

Practice

1. Which statement correctly describes the output behavior of a Moore machine compared to a Mealy machine?

easy

A. Moore machine output depends only on the current state, while Mealy machine output depends on state and input.

B. Moore machine output depends on input only, Mealy machine output depends on current state only.

C. Both Moore and Mealy machines output depend only on the current input.

D. Moore machine output changes immediately with input, Mealy output changes only on clock edges.

Solution

1. Step 1: Understand Moore machine output dependency

   Moore machine outputs depend solely on the current state, not directly on inputs.

2. Step 2: Understand Mealy machine output dependency

   Mealy machine outputs depend on both the current state and the current input, allowing immediate output changes.

3. Final Answer:

   Moore machine output depends only on the current state, while Mealy machine output depends on state and input. -> Option A

4. Quick Check:

   Moore = state-only output, Mealy = state + input output [OK]

Hint: Moore = state only; Mealy = state plus input [OK]

Common Mistakes:

• Confusing output dependency on input for Moore machine
• Thinking Mealy output changes only on clock edges
• Assuming both machines output depend only on input

2. Which Verilog code snippet correctly models a Moore machine output?

easy

A. always @(input or state) output = input & state;

B. always @(posedge clk) output <= state;

C. always @(posedge clk or input) output <= input;

D. always @(input) output = state;

Solution

1. Step 1: Identify Moore machine output timing

   Moore machine outputs update only on clock edges, so output assignment must be inside a posedge clk block.

2. Step 2: Check code snippets for correct output assignment

   always @(posedge clk) output <= state; uses 'always @(posedge clk)' and assigns output from state, matching Moore behavior.

3. Final Answer:

   always @(posedge clk) output <= state; -> Option B

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output inside posedge clk block [OK]

Common Mistakes:

• Using input sensitivity in Moore output block
• Assigning output directly from input in Moore machine
• Using combinational always block for Moore output

3. Given the following Verilog snippet for a Mealy machine output, what is the output when state = 1 and input = 0?

always @(state or input) begin
  if (state == 1)
    output = input;
  else
    output = 1;
end

medium

A. 1

B. Undefined

C. 0

D. Z (high impedance)

Solution

1. Step 1: Analyze condition when state = 1

   The if condition 'state == 1' is true, so output = input.

2. Step 2: Substitute input value

   Input is 0, so output = 0.

3. Final Answer:

   0 -> Option C

4. Quick Check:

   Mealy output depends on state and input, output = 0 [OK]

Hint: Check state condition first, then assign output [OK]

Common Mistakes:

• Ignoring input value when state is 1
• Assuming output is always 1
• Confusing Mealy output with Moore output

4. Identify the error in this Verilog code snippet intended to model a Moore machine output:

always @(input or state) begin
  output = state;
end

medium

A. Output assignment should use non-blocking '<=' operator.

B. Output should depend on input, not state.

C. The sensitivity list should include only input, not state.

D. Output should be assigned only on clock edge, not on input or state changes.

Solution

1. Step 1: Recall Moore machine output timing

   Moore machine outputs update only on clock edges, not on input or state changes directly.

2. Step 2: Check sensitivity list and assignment timing

   The sensitivity list includes input and state, causing output to update asynchronously, which is incorrect for Moore.

3. Final Answer:

   Output should be assigned only on clock edge, not on input or state changes. -> Option D

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output must update only on clock edge [OK]

Common Mistakes:

• Using combinational always block for Moore output
• Ignoring clock in sensitivity list
• Confusing blocking and non-blocking assignments

5. You want to design a state machine in Verilog where the output must change immediately when the input changes, but also depend on the current state. Which machine type should you choose and why?

hard

A. Mealy machine, because output depends on state and input and can change immediately.

B. Moore machine, because it is simpler to implement and faster to respond.

C. Moore machine, because output depends only on state and changes on clock edges.

D. Neither, because outputs cannot depend on inputs in state machines.

Solution

1. Step 1: Understand output timing requirements

   The output must change immediately when input changes, so it cannot wait for clock edges.

2. Step 2: Match machine type to output behavior

   Mealy machine outputs depend on both state and input and can change immediately with input changes, fitting the requirement.

3. Final Answer:

   Mealy machine, because output depends on state and input and can change immediately. -> Option A

4. Quick Check:

   Immediate output change with input = Mealy machine [OK]

Hint: Immediate output change with input means Mealy machine [OK]

Common Mistakes:

• Choosing Moore machine for immediate output change
• Thinking Moore machine outputs depend on input
• Believing outputs cannot depend on inputs in state machines