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Verilogprogramming~20 mins

Moore machine vs Mealy machine in Verilog - Practice Questions

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Challenge - 5 Problems
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Predict Output
intermediate
2:00remaining
Output behavior of a Moore machine
Consider this Verilog code snippet of a Moore machine. What is the output y when the input x changes from 0 to 1?
Verilog
module moore_example(input clk, input x, output reg y);
  reg state;
  always @(posedge clk) begin
    case(state)
      0: if (x) state <= 1;
      1: if (!x) state <= 0;
    endcase
  end
  always @(state) begin
    case(state)
      0: y = 0;
      1: y = 1;
    endcase
  end
endmodule
AOutput y changes immediately when x changes at clock edge.
BOutput y never changes regardless of input x.
COutput y changes only after the clock edge following the input change.
DOutput y changes asynchronously with input x.
Attempts:
2 left
💡 Hint
Remember that in a Moore machine, outputs depend only on the current state, not directly on inputs.
Predict Output
intermediate
2:00remaining
Output behavior of a Mealy machine
Given this Verilog code snippet of a Mealy machine, what is the output y when input x changes from 0 to 1?
Verilog
module mealy_example(input clk, input x, output reg y);
  reg state;
  always @(posedge clk) begin
    case(state)
      0: if (x) state <= 1;
      1: if (!x) state <= 0;
    endcase
  end
  always @(*) begin
    case(state)
      0: y = x;
      1: y = ~x;
    endcase
  end
endmodule
AOutput y changes only when state changes.
BOutput y changes immediately when input x changes.
COutput y changes only after the clock edge following the input change.
DOutput y never changes regardless of input x.
Attempts:
2 left
💡 Hint
In a Mealy machine, outputs depend on both state and inputs.
🧠 Conceptual
advanced
2:00remaining
Difference in output timing between Moore and Mealy machines
Which statement correctly describes the difference in output timing between Moore and Mealy machines?
AMoore machine outputs change only on clock edges; Mealy machine outputs can change asynchronously with inputs.
BMoore machine outputs change asynchronously with inputs; Mealy machine outputs change only on clock edges.
CBoth Moore and Mealy machine outputs change only on clock edges.
DBoth Moore and Mealy machine outputs change asynchronously with inputs.
Attempts:
2 left
💡 Hint
Think about when outputs are updated in each machine type.
🔧 Debug
advanced
2:00remaining
Identify the error in this Mealy machine Verilog code
This Verilog code is intended to implement a Mealy machine. What error will it cause?
Verilog
module mealy_bug(input clk, input x, output reg y);
  reg state;
  always @(posedge clk) begin
    case(state)
      0: if (x) state <= 1;
      1: if (!x) state <= 0;
    endcase
  end
  always @(state) begin
    case(state)
      0: y = x;
      1: y = ~x;
    endcase
  end
endmodule
ANo error; code works as intended.
BOutput y does not update immediately when input x changes.
CSyntax error due to missing initial state assignment.
DOutput y is not updated correctly because it depends on input x but is only sensitive to state.
Attempts:
2 left
💡 Hint
Check the sensitivity list of the output logic block.
🚀 Application
expert
3:00remaining
Design choice for output stability in FSM
You need to design a finite state machine in Verilog where output glitches must be avoided and outputs should be stable during the clock cycle. Which machine type is best suited and why?
AMoore machine, because outputs depend only on state and change synchronously with clock edges.
BMealy machine, because outputs depend on inputs and can change immediately, reducing latency.
CMealy machine, because outputs are stable during the clock cycle.
DMoore machine, because outputs change asynchronously with inputs.
Attempts:
2 left
💡 Hint
Consider output stability and timing in your choice.