Challenge - 5 Problems
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❓ Predict Output
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Output behavior of a Moore machine
Consider this Verilog code snippet of a Moore machine. What is the output
y when the input x changes from 0 to 1?Verilog
module moore_example(input clk, input x, output reg y); reg state; always @(posedge clk) begin case(state) 0: if (x) state <= 1; 1: if (!x) state <= 0; endcase end always @(state) begin case(state) 0: y = 0; 1: y = 1; endcase end endmodule
Attempts:
2 left
💡 Hint
Remember that in a Moore machine, outputs depend only on the current state, not directly on inputs.
✗ Incorrect
In a Moore machine, outputs depend solely on the current state. The state updates on the clock edge based on input x. Therefore, output y changes only after the state updates at the clock edge, not immediately when x changes.
❓ Predict Output
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Output behavior of a Mealy machine
Given this Verilog code snippet of a Mealy machine, what is the output
y when input x changes from 0 to 1?Verilog
module mealy_example(input clk, input x, output reg y); reg state; always @(posedge clk) begin case(state) 0: if (x) state <= 1; 1: if (!x) state <= 0; endcase end always @(*) begin case(state) 0: y = x; 1: y = ~x; endcase end endmodule
Attempts:
2 left
💡 Hint
In a Mealy machine, outputs depend on both state and inputs.
✗ Incorrect
In a Mealy machine, outputs depend on the current state and the current inputs. Since output y is assigned in a combinational block sensitive to inputs, it changes immediately when input x changes.
🧠 Conceptual
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Difference in output timing between Moore and Mealy machines
Which statement correctly describes the difference in output timing between Moore and Mealy machines?
Attempts:
2 left
💡 Hint
Think about when outputs are updated in each machine type.
✗ Incorrect
Moore machine outputs depend only on the state, which updates on clock edges, so outputs change only at clock edges. Mealy machine outputs depend on state and inputs, so outputs can change immediately when inputs change.
🔧 Debug
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Identify the error in this Mealy machine Verilog code
This Verilog code is intended to implement a Mealy machine. What error will it cause?
Verilog
module mealy_bug(input clk, input x, output reg y); reg state; always @(posedge clk) begin case(state) 0: if (x) state <= 1; 1: if (!x) state <= 0; endcase end always @(state) begin case(state) 0: y = x; 1: y = ~x; endcase end endmodule
Attempts:
2 left
💡 Hint
Check the sensitivity list of the output logic block.
✗ Incorrect
The output y depends on input x but the always block is sensitive only to state changes. This means y will not update immediately when x changes, causing incorrect behavior for a Mealy machine.
🚀 Application
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Design choice for output stability in FSM
You need to design a finite state machine in Verilog where output glitches must be avoided and outputs should be stable during the clock cycle. Which machine type is best suited and why?
Attempts:
2 left
💡 Hint
Consider output stability and timing in your choice.
✗ Incorrect
Moore machines produce outputs based only on the current state, which changes synchronously on clock edges. This ensures outputs are stable and free from glitches during the clock cycle, making Moore machines suitable for designs requiring stable outputs.