Moore machine vs Mealy machine in Verilog - Hands-On Comparison

Moore machine vs Mealy machine in Verilog

📖 Scenario: You are designing simple digital circuits that react to inputs and produce outputs. Two common ways to design these circuits are called Moore machines and Mealy machines. Both use states and inputs, but they differ in when and how they produce outputs.

🎯 Goal: Build two simple state machines in Verilog: one Moore machine and one Mealy machine. Both will detect a specific input pattern and produce an output signal. You will see how the output timing differs between the two types.

📋 What You'll Learn

Create a Moore machine with 2 states and output depending only on the state

Create a Mealy machine with 2 states and output depending on state and input

Use a clock and reset signal in both machines

Show output signals for both machines

💡 Why This Matters

🌍 Real World

Moore and Mealy machines are used in digital electronics to design controllers, communication protocols, and user interfaces where outputs depend on sequences of inputs.

💼 Career

Understanding these machines is essential for hardware engineers, FPGA developers, and embedded systems programmers who design reliable and efficient digital circuits.

1

Create the Moore machine states and input

Create a Verilog module called moore_machine with inputs clk, rst, and in. Declare a 1-bit output called out. Inside, create a 1-bit register called state. Define two states: S0 = 0 and S1 = 1. Initialize state to S0 on reset.

Verilog

module moore_machine(input clk, input rst, input in, output reg out);
  // Define states
  // Your code here
endmodule

Need a hint?

Use localparam to define states. Use an always block triggered by clock and reset to update state. Output depends only on state.

2

Create the Mealy machine states and input

Create a Verilog module called mealy_machine with inputs clk, rst, and in. Declare a 1-bit output called out. Inside, create a 1-bit register called state. Define two states: S0 = 0 and S1 = 1. Initialize state to S0 on reset.

Verilog

module mealy_machine(input clk, input rst, input in, output reg out);
  // Define states
  // Your code here
endmodule

Need a hint?

Output depends on both state and in. Use a combinational always block with case to set out.

3

Add testbench signals and clock generation

Create a testbench module called testbench. Declare reg clk, rst, and in. Declare wires moore_out and mealy_out. Instantiate moore_machine and mealy_machine with these signals. Initialize clk to 0 and toggle it every 5 time units. Initialize rst to 1 for 10 time units, then 0. Set in to 0 initially.

Verilog

module testbench;
  // Declare signals
  // Your code here
endmodule

Need a hint?

Use reg for inputs and wire for outputs. Instantiate both machines with the same signals. Use always #5 clk = ~clk; to create a clock.

4

Simulate input changes and display outputs

In the testbench module, add an initial block after reset deassertion. Change in to 1 at 20 time units, then back to 0 at 40 time units, then 1 at 60 time units. Use $monitor to print time, in, moore_out, and mealy_out whenever they change.

Verilog

module testbench;
  reg clk = 0;
  reg rst = 1;
  reg in = 0;
  wire moore_out;
  wire mealy_out;

  moore_machine moore(clk, rst, in, moore_out);
  mealy_machine mealy(clk, rst, in, mealy_out);

  always #5 clk = ~clk;

  initial begin
    #10 rst = 0;
    // Your code here
  end
endmodule

Need a hint?

Use $monitor to print changes. Change in at specified times to see output differences.