Moore machine vs Mealy machine in Verilog - Hands-On Comparison

Moore machine vs Mealy machine in Verilog

📖 Scenario: You are designing simple digital circuits that react to inputs and produce outputs. Two common ways to design these circuits are called Moore machines and Mealy machines. Both use states and inputs, but they differ in when and how they produce outputs.

🎯 Goal: Build two simple state machines in Verilog: one Moore machine and one Mealy machine. Both will detect a specific input pattern and produce an output signal. You will see how the output timing differs between the two types.

📋 What You'll Learn

Create a Moore machine with 2 states and output depending only on the state

Create a Mealy machine with 2 states and output depending on state and input

Use a clock and reset signal in both machines

Show output signals for both machines

💡 Why This Matters

🌍 Real World

Moore and Mealy machines are used in digital electronics to design controllers, communication protocols, and user interfaces where outputs depend on sequences of inputs.

💼 Career

Understanding these machines is essential for hardware engineers, FPGA developers, and embedded systems programmers who design reliable and efficient digital circuits.

1

Create the Moore machine states and input

Create a Verilog module called moore_machine with inputs clk, rst, and in. Declare a 1-bit output called out. Inside, create a 1-bit register called state. Define two states: S0 = 0 and S1 = 1. Initialize state to S0 on reset.

Verilog

module moore_machine(input clk, input rst, input in, output reg out);
  // Define states
  // Your code here
endmodule

Hint

Use localparam to define states. Use an always block triggered by clock and reset to update state. Output depends only on state.

2

Create the Mealy machine states and input

Create a Verilog module called mealy_machine with inputs clk, rst, and in. Declare a 1-bit output called out. Inside, create a 1-bit register called state. Define two states: S0 = 0 and S1 = 1. Initialize state to S0 on reset.

Verilog

module mealy_machine(input clk, input rst, input in, output reg out);
  // Define states
  // Your code here
endmodule

Hint

Output depends on both state and in. Use a combinational always block with case to set out.

3

Add testbench signals and clock generation

Create a testbench module called testbench. Declare reg clk, rst, and in. Declare wires moore_out and mealy_out. Instantiate moore_machine and mealy_machine with these signals. Initialize clk to 0 and toggle it every 5 time units. Initialize rst to 1 for 10 time units, then 0. Set in to 0 initially.

Verilog

module testbench;
  // Declare signals
  // Your code here
endmodule

Hint

Use reg for inputs and wire for outputs. Instantiate both machines with the same signals. Use always #5 clk = ~clk; to create a clock.

4

Simulate input changes and display outputs

In the testbench module, add an initial block after reset deassertion. Change in to 1 at 20 time units, then back to 0 at 40 time units, then 1 at 60 time units. Use $monitor to print time, in, moore_out, and mealy_out whenever they change.

Verilog

module testbench;
  reg clk = 0;
  reg rst = 1;
  reg in = 0;
  wire moore_out;
  wire mealy_out;

  moore_machine moore(clk, rst, in, moore_out);
  mealy_machine mealy(clk, rst, in, mealy_out);

  always #5 clk = ~clk;

  initial begin
    #10 rst = 0;
    // Your code here
  end
endmodule

Hint

Use $monitor to print changes. Change in at specified times to see output differences.

Practice

1. Which statement correctly describes the output behavior of a Moore machine compared to a Mealy machine?

easy

A. Moore machine output depends only on the current state, while Mealy machine output depends on state and input.

B. Moore machine output depends on input only, Mealy machine output depends on current state only.

C. Both Moore and Mealy machines output depend only on the current input.

D. Moore machine output changes immediately with input, Mealy output changes only on clock edges.

Solution

1. Step 1: Understand Moore machine output dependency

   Moore machine outputs depend solely on the current state, not directly on inputs.

2. Step 2: Understand Mealy machine output dependency

   Mealy machine outputs depend on both the current state and the current input, allowing immediate output changes.

3. Final Answer:

   Moore machine output depends only on the current state, while Mealy machine output depends on state and input. -> Option A

4. Quick Check:

   Moore = state-only output, Mealy = state + input output [OK]

Hint: Moore = state only; Mealy = state plus input [OK]

Common Mistakes:

• Confusing output dependency on input for Moore machine
• Thinking Mealy output changes only on clock edges
• Assuming both machines output depend only on input

2. Which Verilog code snippet correctly models a Moore machine output?

easy

A. always @(input or state) output = input & state;

B. always @(posedge clk) output <= state;

C. always @(posedge clk or input) output <= input;

D. always @(input) output = state;

Solution

1. Step 1: Identify Moore machine output timing

   Moore machine outputs update only on clock edges, so output assignment must be inside a posedge clk block.

2. Step 2: Check code snippets for correct output assignment

   always @(posedge clk) output <= state; uses 'always @(posedge clk)' and assigns output from state, matching Moore behavior.

3. Final Answer:

   always @(posedge clk) output <= state; -> Option B

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output inside posedge clk block [OK]

Common Mistakes:

• Using input sensitivity in Moore output block
• Assigning output directly from input in Moore machine
• Using combinational always block for Moore output

3. Given the following Verilog snippet for a Mealy machine output, what is the output when state = 1 and input = 0?

always @(state or input) begin
  if (state == 1)
    output = input;
  else
    output = 1;
end

medium

A. 1

B. Undefined

C. 0

D. Z (high impedance)

Solution

1. Step 1: Analyze condition when state = 1

   The if condition 'state == 1' is true, so output = input.

2. Step 2: Substitute input value

   Input is 0, so output = 0.

3. Final Answer:

   0 -> Option C

4. Quick Check:

   Mealy output depends on state and input, output = 0 [OK]

Hint: Check state condition first, then assign output [OK]

Common Mistakes:

• Ignoring input value when state is 1
• Assuming output is always 1
• Confusing Mealy output with Moore output

4. Identify the error in this Verilog code snippet intended to model a Moore machine output:

always @(input or state) begin
  output = state;
end

medium

A. Output assignment should use non-blocking '<=' operator.

B. Output should depend on input, not state.

C. The sensitivity list should include only input, not state.

D. Output should be assigned only on clock edge, not on input or state changes.

Solution

1. Step 1: Recall Moore machine output timing

   Moore machine outputs update only on clock edges, not on input or state changes directly.

2. Step 2: Check sensitivity list and assignment timing

   The sensitivity list includes input and state, causing output to update asynchronously, which is incorrect for Moore.

3. Final Answer:

   Output should be assigned only on clock edge, not on input or state changes. -> Option D

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output must update only on clock edge [OK]

Common Mistakes:

• Using combinational always block for Moore output
• Ignoring clock in sensitivity list
• Confusing blocking and non-blocking assignments

5. You want to design a state machine in Verilog where the output must change immediately when the input changes, but also depend on the current state. Which machine type should you choose and why?

hard

A. Mealy machine, because output depends on state and input and can change immediately.

B. Moore machine, because it is simpler to implement and faster to respond.

C. Moore machine, because output depends only on state and changes on clock edges.

D. Neither, because outputs cannot depend on inputs in state machines.

Solution

1. Step 1: Understand output timing requirements

   The output must change immediately when input changes, so it cannot wait for clock edges.

2. Step 2: Match machine type to output behavior

   Mealy machine outputs depend on both state and input and can change immediately with input changes, fitting the requirement.

3. Final Answer:

   Mealy machine, because output depends on state and input and can change immediately. -> Option A

4. Quick Check:

   Immediate output change with input = Mealy machine [OK]

Hint: Immediate output change with input means Mealy machine [OK]

Common Mistakes:

• Choosing Moore machine for immediate output change
• Thinking Moore machine outputs depend on input
• Believing outputs cannot depend on inputs in state machines