Moore machine vs Mealy machine in Verilog - Quick Revision & Key Differences

Recall & Review

beginner

What is a Moore machine in digital design?

A Moore machine is a finite state machine where the outputs depend only on the current state, not on the inputs.

beginner

What is a Mealy machine in digital design?

A Mealy machine is a finite state machine where the outputs depend on both the current state and the current inputs.

intermediate

How does output timing differ between Moore and Mealy machines?

In Moore machines, outputs change only on state transitions (clock edges). In Mealy machines, outputs can change immediately when inputs change, even between clock edges.

intermediate

Which machine generally has fewer states: Moore or Mealy?

Mealy machines generally have fewer states because outputs depend on inputs as well, reducing the need for extra states.

advanced

Write a simple Verilog snippet showing output assignment in a Moore machine.

always @(posedge clk or posedge reset) begin if (reset) state <= S0; else state <= next_state; end always @(state) begin case(state) S0: output_signal = 0; S1: output_signal = 1; default: output_signal = 0; endcase end

In a Moore machine, the output depends on:

A Only the current state

B Only the current input

C Current state and input

D Previous state

Moore machine outputs depend only on the current state, not on inputs.

Which machine can change output immediately when input changes?

A Moore machine

B Mealy machine

C Both Moore and Mealy

D Neither

Mealy machine outputs depend on inputs and can change immediately when inputs change.

Which machine usually requires fewer states?

A Depends on clock speed

B Moore machine

C Both require the same

D Mealy machine

Mealy machines often have fewer states because outputs depend on inputs as well.

In Verilog, where is the output assigned in a Moore machine?

A Inside the state transition block

B Outside any always block

C Inside a block sensitive only to state changes

D Inside the input change block

In Moore machines, outputs are assigned based on state, so the block is sensitive to state changes.

Which machine's output is synchronous with the clock?

A Moore machine

B Mealy machine

C Both

D Neither

Moore machine outputs change synchronously with state transitions, which are clocked.

Explain the main difference between Moore and Mealy machines in terms of output dependency.

Think about when outputs can change in each machine.

Describe how you would implement output logic differently in Verilog for a Moore machine versus a Mealy machine.

Consider sensitivity lists and when outputs update.

Practice

1. Which statement correctly describes the output behavior of a Moore machine compared to a Mealy machine?

easy

A. Moore machine output depends only on the current state, while Mealy machine output depends on state and input.

B. Moore machine output depends on input only, Mealy machine output depends on current state only.

C. Both Moore and Mealy machines output depend only on the current input.

D. Moore machine output changes immediately with input, Mealy output changes only on clock edges.

Solution

1. Step 1: Understand Moore machine output dependency

   Moore machine outputs depend solely on the current state, not directly on inputs.

2. Step 2: Understand Mealy machine output dependency

   Mealy machine outputs depend on both the current state and the current input, allowing immediate output changes.

3. Final Answer:

   Moore machine output depends only on the current state, while Mealy machine output depends on state and input. -> Option A

4. Quick Check:

   Moore = state-only output, Mealy = state + input output [OK]

Hint: Moore = state only; Mealy = state plus input [OK]

Common Mistakes:

• Confusing output dependency on input for Moore machine
• Thinking Mealy output changes only on clock edges
• Assuming both machines output depend only on input

2. Which Verilog code snippet correctly models a Moore machine output?

easy

A. always @(input or state) output = input & state;

B. always @(posedge clk) output <= state;

C. always @(posedge clk or input) output <= input;

D. always @(input) output = state;

Solution

1. Step 1: Identify Moore machine output timing

   Moore machine outputs update only on clock edges, so output assignment must be inside a posedge clk block.

2. Step 2: Check code snippets for correct output assignment

   always @(posedge clk) output <= state; uses 'always @(posedge clk)' and assigns output from state, matching Moore behavior.

3. Final Answer:

   always @(posedge clk) output <= state; -> Option B

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output inside posedge clk block [OK]

Common Mistakes:

• Using input sensitivity in Moore output block
• Assigning output directly from input in Moore machine
• Using combinational always block for Moore output

3. Given the following Verilog snippet for a Mealy machine output, what is the output when state = 1 and input = 0?

always @(state or input) begin
  if (state == 1)
    output = input;
  else
    output = 1;
end

medium

A. 1

B. Undefined

C. 0

D. Z (high impedance)

Solution

1. Step 1: Analyze condition when state = 1

   The if condition 'state == 1' is true, so output = input.

2. Step 2: Substitute input value

   Input is 0, so output = 0.

3. Final Answer:

   0 -> Option C

4. Quick Check:

   Mealy output depends on state and input, output = 0 [OK]

Hint: Check state condition first, then assign output [OK]

Common Mistakes:

• Ignoring input value when state is 1
• Assuming output is always 1
• Confusing Mealy output with Moore output

4. Identify the error in this Verilog code snippet intended to model a Moore machine output:

always @(input or state) begin
  output = state;
end

medium

A. Output assignment should use non-blocking '<=' operator.

B. Output should depend on input, not state.

C. The sensitivity list should include only input, not state.

D. Output should be assigned only on clock edge, not on input or state changes.

Solution

1. Step 1: Recall Moore machine output timing

   Moore machine outputs update only on clock edges, not on input or state changes directly.

2. Step 2: Check sensitivity list and assignment timing

   The sensitivity list includes input and state, causing output to update asynchronously, which is incorrect for Moore.

3. Final Answer:

   Output should be assigned only on clock edge, not on input or state changes. -> Option D

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output must update only on clock edge [OK]

Common Mistakes:

• Using combinational always block for Moore output
• Ignoring clock in sensitivity list
• Confusing blocking and non-blocking assignments

5. You want to design a state machine in Verilog where the output must change immediately when the input changes, but also depend on the current state. Which machine type should you choose and why?

hard

A. Mealy machine, because output depends on state and input and can change immediately.

B. Moore machine, because it is simpler to implement and faster to respond.

C. Moore machine, because output depends only on state and changes on clock edges.

D. Neither, because outputs cannot depend on inputs in state machines.

Solution

1. Step 1: Understand output timing requirements

   The output must change immediately when input changes, so it cannot wait for clock edges.

2. Step 2: Match machine type to output behavior

   Mealy machine outputs depend on both state and input and can change immediately with input changes, fitting the requirement.

3. Final Answer:

   Mealy machine, because output depends on state and input and can change immediately. -> Option A

4. Quick Check:

   Immediate output change with input = Mealy machine [OK]

Hint: Immediate output change with input means Mealy machine [OK]

Common Mistakes:

• Choosing Moore machine for immediate output change
• Thinking Moore machine outputs depend on input
• Believing outputs cannot depend on inputs in state machines