Moore machine vs Mealy machine in Verilog - Performance Comparison

Time Complexity: Moore machine vs Mealy machine

O(n)

Understanding Time Complexity

We want to see how the time to run Moore and Mealy machines changes as inputs grow.

How does the design affect the number of steps the machine takes?

Scenario Under Consideration

Analyze the time complexity of the following Verilog Moore and Mealy machine snippets.

// Moore machine example
always @(posedge clk) begin
  state <= next_state;
  output_signal <= state_output;
end

// Mealy machine example
always @(posedge clk) begin
  state <= next_state;
  output_signal <= output_logic(input_signal, state);
end
    

These snippets show how outputs depend on state only (Moore) or state and input (Mealy).

Identify Repeating Operations

Both machines update state and output every clock cycle.

• Primary operation: State update and output assignment on each clock edge.
• How many times: Once per clock cycle, repeated for each input event.

How Execution Grows With Input

Each input triggers one state and output update, so operations grow linearly with input size.

Input Size (n)	Approx. Operations
10	10 state and output updates
100	100 state and output updates
1000	1000 state and output updates

Pattern observation: Operations increase directly with input size, no extra loops inside.

Final Time Complexity

Time Complexity: O(n)

This means the time grows in a straight line as inputs increase, one step per input.

Common Mistake

[X] Wrong: "Mealy machines are always faster because outputs change immediately."

[OK] Correct: Both machines update outputs every clock cycle, so speed depends on clock, not output logic style.

Interview Connect

Understanding how Moore and Mealy machines handle inputs helps you explain timing and design choices clearly in real projects.

Self-Check

"What if the Mealy machine had multiple inputs changing asynchronously? How would that affect time complexity?"