Linear Feedback Shift Register (LFSR) in Verilog - Step-by-Step Execution

Concept Flow - Linear Feedback Shift Register (LFSR)

Initialize shift register with seed

↓

Shift bits right by 1 position

↓

Calculate feedback bit by XOR of selected bits

↓

Insert feedback bit at leftmost position

↓

Output current register value

↓

Repeat for next clock cycle

The LFSR shifts bits each cycle, calculates a new bit by XORing certain bits, inserts it, and outputs the register value repeatedly.

Execution Sample

Verilog

module lfsr(
  input clk,
  input reset,
  output reg [3:0] q
);
  always @(posedge clk or posedge reset) begin
    if (reset) q <= 4'b1001;
    else q <= {q[3] ^ q[2], q[3:1]};
  end
endmodule

A 4-bit LFSR that shifts bits right and inserts XOR of bits 3 and 2 at left on each clock.

Execution Table

Cycle	Register q (binary)	Feedback bit (q[3]^q[2])	Action	Output q
0	1001	-	Reset sets q to 1001	1001
1	1001	1	Shift right, insert feedback 1	1100
2	1100	1	Shift right, insert feedback 1	1110
3	1110	0	Shift right, insert feedback 0	0111
4	0111	1	Shift right, insert feedback 1	1011
5	1011	1	Shift right, insert feedback 1	1101
6	1101	0	Shift right, insert feedback 0	0110
7	0110	1	Shift right, insert feedback 1	1011
8	1011	1	Shift right, insert feedback 1	1101
9	1101	0	Shift right, insert feedback 0	0110
10	0110	1	Shift right, insert feedback 1	1011
Exit	-	-	Full period is 15 cycles before returning to 1001	-

💡 The LFSR produces a maximum-length sequence of 15 states before repeating.

Variable Tracker

Variable	Start (Cycle 0)	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10
q	1001	1100	1110	0111	1011	1101	0110	1011	1101	0110	1011
feedback bit	-	1	1	0	1	1	0	1	1	0	1

Key Moments - 3 Insights

Why does the feedback bit use XOR of q[3] and q[2]?

The feedback bit is calculated by XORing specific bits (q[3] and q[2]) to create a pseudo-random sequence; this is shown in the execution_table column 'Feedback bit' where each cycle's feedback depends on those bits.

Why does the register value repeat after some cycles?

Because the LFSR has a fixed size and feedback, it cycles through a sequence of states; the full period is 15 cycles before repeating, as shown in the exit note of the execution_table.

What happens on reset in the LFSR?

On reset, the register q is set to the initial seed 1001, as shown in cycle 0 of the execution_table, restarting the sequence.

Visual Quiz - 3 Questions

Look at the execution_table at cycle 3, what is the feedback bit?

A 0

B 1

C Undefined

D 3

💡 Hint

Check the 'Feedback bit' column for cycle 3 in the execution_table.

At which cycle does the register first become 0111?

A Cycle 1

B Cycle 3

C Cycle 2

D Cycle 4

💡 Hint

Look at the 'Register q (binary)' column in the execution_table.

If the feedback was changed to XOR of q[3] and q[1], how would the feedback bit at cycle 1 change?

A It would be undefined

B It would be 1

C It would be same as original

D It would be 0

💡 Hint

Compare bits q[3] and q[1] at cycle 0 from variable_tracker to calculate new feedback.

Concept Snapshot

Linear Feedback Shift Register (LFSR):
- A shift register that shifts bits each clock cycle.
- Feedback bit is XOR of selected bits (e.g., q[3]^q[2]).
- Feedback bit inserted at leftmost position after shift.
- Produces pseudo-random sequence cycling through states.
- Reset initializes register to a seed value.

Full Transcript

This visual execution shows a 4-bit Linear Feedback Shift Register (LFSR) in Verilog. The register q starts at 1001 on reset. Each clock cycle, the bits shift right by one position. The new leftmost bit is the XOR of bits q[3] and q[2]. The execution table traces each cycle's register value, feedback bit, and action. The variable tracker shows how q and feedback bit change over cycles. Key moments clarify why XOR is used for feedback, why the sequence repeats, and the effect of reset. The quiz tests understanding of feedback bit calculation, register values at cycles, and how changing feedback taps affects output. The snapshot summarizes the LFSR behavior and structure for quick reference.