Linear Feedback Shift Register (LFSR) in Verilog - Mini Project: Build & Apply

Linear Feedback Shift Register (LFSR) in Verilog

📖 Scenario: You are designing a simple digital circuit that generates a sequence of bits using a Linear Feedback Shift Register (LFSR). This is useful in hardware for creating pseudo-random sequences, which can be used in testing or encryption.

🎯 Goal: Build a 4-bit LFSR module in Verilog that shifts bits on each clock cycle and uses feedback from specific bits to generate the next bit in the sequence.

📋 What You'll Learn

Create a 4-bit register to hold the LFSR state

Use XOR feedback from bit 3 and bit 2 to generate the new input bit

Shift the register bits on each positive clock edge

Output the current LFSR state

💡 Why This Matters

🌍 Real World

LFSRs are used in hardware for generating pseudo-random numbers, built-in self-test circuits, and scrambling data streams.

💼 Career

Understanding LFSRs is important for hardware engineers working on digital design, FPGA programming, and embedded systems testing.

1

Create the 4-bit register for LFSR state

Write a Verilog module named lfsr with inputs clk and reset, and an output reg [3:0] state. Inside the module, declare a 4-bit register called state to hold the LFSR bits.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
// Declare the 4-bit register state
// Your code here
endmodule

Hint

Start by defining the module and its inputs and outputs. Declare state as a 4-bit register inside the module.

2

Initialize the LFSR state on reset

Inside the lfsr module, add an always @(posedge clk or posedge reset) block. When reset is high, set state to 4'b0001 to start the sequence.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            // Initialize state to 4'b0001
            // Your code here
        end
    end
endmodule

Hint

Use a clocked always block that also triggers on reset. When reset is high, assign 4'b0001 to state.

3

Add feedback and shift logic for LFSR

Inside the always block, add an else clause. Compute a new bit called feedback as the XOR of state[3] and state[2]. Then shift state left by 1 and set state[0] to feedback.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= 4'b0001;
        end else begin
            // Calculate feedback as XOR of state[3] and state[2]
            // Shift state left by 1 and insert feedback at state[0]
            // Your code here
        end
    end
endmodule

Hint

Use a wire to hold the XOR of bits 3 and 2. Then shift the register left and add the feedback bit at the right end.

4

Display the LFSR state output

Add a testbench module named testbench that instantiates the lfsr module. In the testbench, generate a clock signal and toggle reset once at the start. Run the clock for 10 cycles and use $display to print the state value on each clock cycle.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= 4'b0001;
        end else begin
            wire feedback = state[3] ^ state[2];
            state <= {state[2:0], feedback};
        end
    end
endmodule

// Create testbench module
// Your code here

Hint

Create a testbench that toggles the clock and reset signals. Use $display to print the LFSR state on each clock cycle.

Practice

1.

What is the main purpose of a Linear Feedback Shift Register (LFSR) in digital circuits?

easy

A. To store large amounts of data

B. To perform arithmetic addition

C. To convert analog signals to digital

D. To generate a pseudo-random sequence of bits

Solution

1. Step 1: Understand LFSR function

   An LFSR uses shift and XOR feedback to produce a sequence of bits that appears random.

2. Step 2: Identify main use

   This sequence is used for pseudo-random number generation and testing, not arithmetic or storage.

3. Final Answer:

   To generate a pseudo-random sequence of bits -> Option D

4. Quick Check:

   LFSR = pseudo-random bit generator [OK]

Hint: LFSR creates random-like bits by shifting and XOR [OK]

Common Mistakes:

• Confusing LFSR with memory storage
• Thinking LFSR does arithmetic
• Assuming LFSR converts analog signals

2.

Which of the following is the correct Verilog syntax to declare a 4-bit register named lfsr?

easy

A. reg [3:0] lfsr;

B. reg lfsr[3:0];

C. wire [4:1] lfsr;

D. reg (3:0) lfsr;

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg [msb:lsb] name; syntax.

2. Step 2: Check each option

   reg [3:0] lfsr; uses correct syntax reg [3:0] lfsr;. reg lfsr[3:0]; uses wrong array style. wire [4:1] lfsr; uses wire, not reg. reg (3:0) lfsr; has invalid parentheses.

3. Final Answer:

   reg [3:0] lfsr; -> Option A

4. Quick Check:

   Correct reg syntax = reg [3:0] lfsr; [OK]

Hint: Use reg [msb:lsb] name; to declare registers [OK]

Common Mistakes:

• Using wire instead of reg for registers
• Incorrect bit range order or syntax
• Using parentheses instead of brackets

3.

Given this Verilog snippet for a 3-bit LFSR with taps at bits 3 and 2:

reg [2:0] lfsr = 3'b001;
always @(posedge clk) begin
  lfsr <= {lfsr[1:0], lfsr[2] ^ lfsr[1]};
end

What is the value of lfsr after 1 clock cycle?

medium

A. 3'b011

B. 3'b010

C. 3'b110

D. 3'b100

Solution

1. Step 1: Calculate first clock cycle

   Initial lfsr = 001. Feedback = lfsr[2]^lfsr[1] = 0^0=0.
   New lfsr = {lfsr[1:0], feedback} = {0,1,0} = 010.

2. Step 2: Confirm value

   After 1 clock cycle, lfsr = 3'b010, which matches 3'b010.

3. Final Answer:

   3'b010 -> Option B

4. Quick Check:

   Shift and XOR feedback = 010 after 1 cycle [OK]

Hint: Track bits step-by-step for each clock cycle [OK]

Common Mistakes:

• Mixing bit order in concatenation
• Calculating feedback incorrectly
• Confusing initial and next states

4.

Identify the error in this Verilog LFSR code snippet:

reg [3:0] lfsr = 4'b0000;
always @(posedge clk) begin
  lfsr <= {lfsr[2:0], lfsr[3] ^ lfsr[0]};
end

medium

A. The register size declaration is wrong

B. The feedback XOR taps are incorrect for 4-bit LFSR

C. Initial value can't be all zeros in LFSR

D. The concatenation order is reversed

Solution

1. Step 1: Check initial value

   LFSRs must not start with all zeros because they will stay stuck at zero forever (no feedback).

2. Step 2: Verify other parts

   Feedback taps and concatenation are valid for a 4-bit LFSR. Register size is correctly declared as 4 bits.

3. Final Answer:

   Initial value can't be all zeros in LFSR -> Option C

4. Quick Check:

   All-zero start = stuck LFSR [OK]

Hint: Never start LFSR with all zeros [OK]

Common Mistakes:

• Using zero initial value
• Misunderstanding feedback tap positions
• Incorrect bit concatenation order

5.

You want to design an 8-bit LFSR in Verilog that cycles through all 255 non-zero states before repeating. Which of the following tap combinations is a valid maximal-length feedback polynomial?

hard

A. Taps at bits 8 and 5 (lfsr[7] and lfsr[4])

B. Taps at bits 8 and 7 (lfsr[7] and lfsr[6])

C. Taps at bits 8 and 6 (lfsr[7] and lfsr[5])

D. Taps at bits 8 and 4 (lfsr[7] and lfsr[3])

Solution

1. Step 1: Recall maximal-length tap sets for 8-bit LFSR

   Common maximal-length taps for 8-bit LFSR are bits 8 and 5 (1-based indexing).

2. Step 2: Match options with known polynomials

   Taps at bits 8 and 5 (lfsr[7] and lfsr[4]) matches a valid maximal-length set. Taps at bits 8 and 7 (lfsr[7] and lfsr[6]), 8 and 6 (lfsr[7] and lfsr[5]), and 8 and 4 (lfsr[7] and lfsr[3]) are not maximal-length taps.

3. Step 3: Check indexing in Verilog (0-based)

   Bits 8 and 5 correspond to lfsr[7] and lfsr[4], which is Taps at bits 8 and 5 (lfsr[7] and lfsr[4]).

4. Final Answer:

   Taps at bits 8 and 5 (lfsr[7] and lfsr[4]) -> Option A

5. Quick Check:

   Maximal taps for 8-bit LFSR = bits 8 and 5 [OK]

Hint: Use known maximal taps like bits 8 and 5 for full cycle [OK]

Common Mistakes:

• Choosing non-maximal tap positions
• Confusing bit indexing (1-based vs 0-based)
• Assuming any two taps produce maximal length