Linear Feedback Shift Register (LFSR) in Verilog - Mini Project: Build & Apply

Linear Feedback Shift Register (LFSR) in Verilog

📖 Scenario: You are designing a simple digital circuit that generates a sequence of bits using a Linear Feedback Shift Register (LFSR). This is useful in hardware for creating pseudo-random sequences, which can be used in testing or encryption.

🎯 Goal: Build a 4-bit LFSR module in Verilog that shifts bits on each clock cycle and uses feedback from specific bits to generate the next bit in the sequence.

📋 What You'll Learn

Create a 4-bit register to hold the LFSR state

Use XOR feedback from bit 3 and bit 2 to generate the new input bit

Shift the register bits on each positive clock edge

Output the current LFSR state

💡 Why This Matters

🌍 Real World

LFSRs are used in hardware for generating pseudo-random numbers, built-in self-test circuits, and scrambling data streams.

💼 Career

Understanding LFSRs is important for hardware engineers working on digital design, FPGA programming, and embedded systems testing.

1

Create the 4-bit register for LFSR state

Write a Verilog module named lfsr with inputs clk and reset, and an output reg [3:0] state. Inside the module, declare a 4-bit register called state to hold the LFSR bits.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
// Declare the 4-bit register state
// Your code here
endmodule

Need a hint?

Start by defining the module and its inputs and outputs. Declare state as a 4-bit register inside the module.

2

Initialize the LFSR state on reset

Inside the lfsr module, add an always @(posedge clk or posedge reset) block. When reset is high, set state to 4'b0001 to start the sequence.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            // Initialize state to 4'b0001
            // Your code here
        end
    end
endmodule

Need a hint?

Use a clocked always block that also triggers on reset. When reset is high, assign 4'b0001 to state.

3

Add feedback and shift logic for LFSR

Inside the always block, add an else clause. Compute a new bit called feedback as the XOR of state[3] and state[2]. Then shift state left by 1 and set state[0] to feedback.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= 4'b0001;
        end else begin
            // Calculate feedback as XOR of state[3] and state[2]
            // Shift state left by 1 and insert feedback at state[0]
            // Your code here
        end
    end
endmodule

Need a hint?

Use a wire to hold the XOR of bits 3 and 2. Then shift the register left and add the feedback bit at the right end.

4

Display the LFSR state output

Add a testbench module named testbench that instantiates the lfsr module. In the testbench, generate a clock signal and toggle reset once at the start. Run the clock for 10 cycles and use $display to print the state value on each clock cycle.

Verilog

module lfsr(input clk, input reset, output reg [3:0] state);
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= 4'b0001;
        end else begin
            wire feedback = state[3] ^ state[2];
            state <= {state[2:0], feedback};
        end
    end
endmodule

// Create testbench module
// Your code here

Need a hint?

Create a testbench that toggles the clock and reset signals. Use $display to print the LFSR state on each clock cycle.