Linear Feedback Shift Register (LFSR) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit LFSR with given taps

What is the output sequence of this 4-bit LFSR after 5 clock cycles?

module lfsr_4bit(
  input clk,
  input rst,
  output reg [3:0] q
);
  wire feedback = q[3] ^ q[2];
  always @(posedge clk or posedge rst) begin
    if (rst) q <= 4'b0001;
    else q <= {q[2:0], feedback};
  end
endmodule

A 0001, 0010, 0100, 1000, 0001

B 0001, 1000, 0100, 0010, 0001

C 0001, 0010, 0100, 1001, 0011

D 0001, 0011, 0111, 1110, 1101

💡 Hint

Think about how the feedback bit is calculated and shifted in.

The feedback is XOR of bits 3 and 2. Starting from 0001, the sequence is generated by shifting the bits such that new state = {q[2:0], feedback}.

🧠 Conceptual

intermediate

Purpose of the feedback bit in an LFSR

What is the main role of the feedback bit in a Linear Feedback Shift Register (LFSR)?

A To count the number of clock cycles

B To introduce new bits based on XOR of selected bits, creating a pseudo-random sequence

C To hold the current state without change

D To reset the register to zero

💡 Hint

Think about how LFSR generates sequences.

The feedback bit is calculated by XORing certain bits of the register to create a new bit that is shifted in, producing a pseudo-random sequence.

🔧 Debug

advanced

Identify the error in this LFSR Verilog code

This 3-bit LFSR code is intended to generate a pseudo-random sequence. What error will it cause when synthesized?

module lfsr_3bit(
  input clk,
  input rst,
  output reg [2:0] q
);
  wire feedback = q[2] ^ q[0];
  always @(posedge clk or posedge rst) begin
    if (rst) q <= 3'b001
    else q <= {q[1:0], feedback};
  end
endmodule

A Syntax error due to missing semicolon after if statement

B Runtime error because feedback is not declared as reg

C No error, code works correctly

D Synthesis error because q is not initialized

💡 Hint

Check the if statement syntax carefully.

The if statement line 'if (rst) q <= 3'b001' is missing a semicolon at the end, causing a syntax error.

❓ Predict Output

advanced

Number of unique states in a 3-bit maximal LFSR

How many unique non-zero states will a 3-bit maximal LFSR cycle through before repeating?
Assume the feedback polynomial is x^3 + x + 1.

A 8

B 6

C 3

D 7

💡 Hint

A maximal LFSR cycles through all possible states except zero.

A 3-bit register has 2^3=8 states. Maximal LFSR cycles through all except the zero state, so 7 unique states.

🚀 Application

expert

Determine the next state of a 5-bit LFSR

Given this 5-bit LFSR with taps at bits 5 and 3 (positions 4 and 2 in zero-based indexing), and current state 10110, what is the next state?

Current state q = 5'b10110
Feedback = q[4] ^ q[2]
Next state = {q[3:0], feedback}

A 01100

B 11011

C 01101

D 10101

💡 Hint

Calculate feedback bit first, then shift left and insert feedback at LSB.

Feedback = q[4] ^ q[2] = 1 ^ 1 = 0. Next state = {q[3:0], feedback} = {0110, 0} = 01100.