Linear Feedback Shift Register (LFSR) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit LFSR with given taps

What is the output sequence of this 4-bit LFSR after 5 clock cycles?

module lfsr_4bit(
  input clk,
  input rst,
  output reg [3:0] q
);
  wire feedback = q[3] ^ q[2];
  always @(posedge clk or posedge rst) begin
    if (rst) q <= 4'b0001;
    else q <= {q[2:0], feedback};
  end
endmodule

A 0001, 0010, 0100, 1000, 0001

B 0001, 1000, 0100, 0010, 0001

C 0001, 0010, 0100, 1001, 0011

D 0001, 0011, 0111, 1110, 1101

💡 Hint

Think about how the feedback bit is calculated and shifted in.

The feedback is XOR of bits 3 and 2. Starting from 0001, the sequence is generated by shifting the bits such that new state = {q[2:0], feedback}.

🧠 Conceptual

intermediate

Purpose of the feedback bit in an LFSR

What is the main role of the feedback bit in a Linear Feedback Shift Register (LFSR)?

A To count the number of clock cycles

B To introduce new bits based on XOR of selected bits, creating a pseudo-random sequence

C To hold the current state without change

D To reset the register to zero

💡 Hint

Think about how LFSR generates sequences.

The feedback bit is calculated by XORing certain bits of the register to create a new bit that is shifted in, producing a pseudo-random sequence.

🔧 Debug

advanced

Identify the error in this LFSR Verilog code

This 3-bit LFSR code is intended to generate a pseudo-random sequence. What error will it cause when synthesized?

module lfsr_3bit(
  input clk,
  input rst,
  output reg [2:0] q
);
  wire feedback = q[2] ^ q[0];
  always @(posedge clk or posedge rst) begin
    if (rst) q <= 3'b001
    else q <= {q[1:0], feedback};
  end
endmodule

A Syntax error due to missing semicolon after if statement

B Runtime error because feedback is not declared as reg

C No error, code works correctly

D Synthesis error because q is not initialized

💡 Hint

Check the if statement syntax carefully.

The if statement line 'if (rst) q <= 3'b001' is missing a semicolon at the end, causing a syntax error.

❓ Predict Output

advanced

Number of unique states in a 3-bit maximal LFSR

How many unique non-zero states will a 3-bit maximal LFSR cycle through before repeating?
Assume the feedback polynomial is x^3 + x + 1.

A 8

B 6

C 3

D 7

💡 Hint

A maximal LFSR cycles through all possible states except zero.

A 3-bit register has 2^3=8 states. Maximal LFSR cycles through all except the zero state, so 7 unique states.

🚀 Application

expert

Determine the next state of a 5-bit LFSR

Given this 5-bit LFSR with taps at bits 5 and 3 (positions 4 and 2 in zero-based indexing), and current state 10110, what is the next state?

Current state q = 5'b10110
Feedback = q[4] ^ q[2]
Next state = {q[3:0], feedback}

A 01100

B 11011

C 01101

D 10101

💡 Hint

Calculate feedback bit first, then shift left and insert feedback at LSB.

Feedback = q[4] ^ q[2] = 1 ^ 1 = 0. Next state = {q[3:0], feedback} = {0110, 0} = 01100.

Practice

1.

What is the main purpose of a Linear Feedback Shift Register (LFSR) in digital circuits?

easy

A. To store large amounts of data

B. To perform arithmetic addition

C. To convert analog signals to digital

D. To generate a pseudo-random sequence of bits

Solution

1. Step 1: Understand LFSR function

   An LFSR uses shift and XOR feedback to produce a sequence of bits that appears random.

2. Step 2: Identify main use

   This sequence is used for pseudo-random number generation and testing, not arithmetic or storage.

3. Final Answer:

   To generate a pseudo-random sequence of bits -> Option D

4. Quick Check:

   LFSR = pseudo-random bit generator [OK]

Hint: LFSR creates random-like bits by shifting and XOR [OK]

Common Mistakes:

• Confusing LFSR with memory storage
• Thinking LFSR does arithmetic
• Assuming LFSR converts analog signals

2.

Which of the following is the correct Verilog syntax to declare a 4-bit register named lfsr?

easy

A. reg [3:0] lfsr;

B. reg lfsr[3:0];

C. wire [4:1] lfsr;

D. reg (3:0) lfsr;

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg [msb:lsb] name; syntax.

2. Step 2: Check each option

   reg [3:0] lfsr; uses correct syntax reg [3:0] lfsr;. reg lfsr[3:0]; uses wrong array style. wire [4:1] lfsr; uses wire, not reg. reg (3:0) lfsr; has invalid parentheses.

3. Final Answer:

   reg [3:0] lfsr; -> Option A

4. Quick Check:

   Correct reg syntax = reg [3:0] lfsr; [OK]

Hint: Use reg [msb:lsb] name; to declare registers [OK]

Common Mistakes:

• Using wire instead of reg for registers
• Incorrect bit range order or syntax
• Using parentheses instead of brackets

3.

Given this Verilog snippet for a 3-bit LFSR with taps at bits 3 and 2:

reg [2:0] lfsr = 3'b001;
always @(posedge clk) begin
  lfsr <= {lfsr[1:0], lfsr[2] ^ lfsr[1]};
end

What is the value of lfsr after 1 clock cycle?

medium

A. 3'b011

B. 3'b010

C. 3'b110

D. 3'b100

Solution

1. Step 1: Calculate first clock cycle

   Initial lfsr = 001. Feedback = lfsr[2]^lfsr[1] = 0^0=0.
   New lfsr = {lfsr[1:0], feedback} = {0,1,0} = 010.

2. Step 2: Confirm value

   After 1 clock cycle, lfsr = 3'b010, which matches 3'b010.

3. Final Answer:

   3'b010 -> Option B

4. Quick Check:

   Shift and XOR feedback = 010 after 1 cycle [OK]

Hint: Track bits step-by-step for each clock cycle [OK]

Common Mistakes:

• Mixing bit order in concatenation
• Calculating feedback incorrectly
• Confusing initial and next states

4.

Identify the error in this Verilog LFSR code snippet:

reg [3:0] lfsr = 4'b0000;
always @(posedge clk) begin
  lfsr <= {lfsr[2:0], lfsr[3] ^ lfsr[0]};
end

medium

A. The register size declaration is wrong

B. The feedback XOR taps are incorrect for 4-bit LFSR

C. Initial value can't be all zeros in LFSR

D. The concatenation order is reversed

Solution

1. Step 1: Check initial value

   LFSRs must not start with all zeros because they will stay stuck at zero forever (no feedback).

2. Step 2: Verify other parts

   Feedback taps and concatenation are valid for a 4-bit LFSR. Register size is correctly declared as 4 bits.

3. Final Answer:

   Initial value can't be all zeros in LFSR -> Option C

4. Quick Check:

   All-zero start = stuck LFSR [OK]

Hint: Never start LFSR with all zeros [OK]

Common Mistakes:

• Using zero initial value
• Misunderstanding feedback tap positions
• Incorrect bit concatenation order

5.

You want to design an 8-bit LFSR in Verilog that cycles through all 255 non-zero states before repeating. Which of the following tap combinations is a valid maximal-length feedback polynomial?

hard

A. Taps at bits 8 and 5 (lfsr[7] and lfsr[4])

B. Taps at bits 8 and 7 (lfsr[7] and lfsr[6])

C. Taps at bits 8 and 6 (lfsr[7] and lfsr[5])

D. Taps at bits 8 and 4 (lfsr[7] and lfsr[3])

Solution

1. Step 1: Recall maximal-length tap sets for 8-bit LFSR

   Common maximal-length taps for 8-bit LFSR are bits 8 and 5 (1-based indexing).

2. Step 2: Match options with known polynomials

   Taps at bits 8 and 5 (lfsr[7] and lfsr[4]) matches a valid maximal-length set. Taps at bits 8 and 7 (lfsr[7] and lfsr[6]), 8 and 6 (lfsr[7] and lfsr[5]), and 8 and 4 (lfsr[7] and lfsr[3]) are not maximal-length taps.

3. Step 3: Check indexing in Verilog (0-based)

   Bits 8 and 5 correspond to lfsr[7] and lfsr[4], which is Taps at bits 8 and 5 (lfsr[7] and lfsr[4]).

4. Final Answer:

   Taps at bits 8 and 5 (lfsr[7] and lfsr[4]) -> Option A

5. Quick Check:

   Maximal taps for 8-bit LFSR = bits 8 and 5 [OK]

Hint: Use known maximal taps like bits 8 and 5 for full cycle [OK]

Common Mistakes:

• Choosing non-maximal tap positions
• Confusing bit indexing (1-based vs 0-based)
• Assuming any two taps produce maximal length