Linear Feedback Shift Register (LFSR) in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Linear Feedback Shift Register (LFSR)?

An LFSR is a shift register where the input bit is a linear function (usually XOR) of its previous state bits. It generates pseudo-random sequences used in testing and cryptography.

beginner

How does feedback work in an LFSR?

Feedback is created by XORing selected bits (called taps) of the register and feeding the result back into the input bit of the shift register.

intermediate

What is the role of 'taps' in an LFSR?

Taps are specific bit positions in the register used to calculate the feedback bit by XOR operation. The choice of taps affects the sequence length and randomness.

intermediate

Write a simple Verilog code snippet for a 4-bit LFSR with taps at bits 4 and 3.

module lfsr_4bit(clk, reset, out); input clk, reset; output reg [3:0] out; wire feedback = out[3] ^ out[2]; always @(posedge clk or posedge reset) begin if (reset) out <= 4'b0001; else out <= {out[2:0], feedback}; end endmodule

beginner

Why is the initial value (seed) important in an LFSR?

The seed sets the starting state of the LFSR. If it is zero, the LFSR will stay at zero and not generate a sequence. A non-zero seed ensures the LFSR cycles through states.

What operation is commonly used to generate the feedback bit in an LFSR?

A OR

B AND

C XOR

D NOT

The feedback bit in an LFSR is typically generated by XORing selected bits (taps) of the register.

What happens if the initial seed of an LFSR is all zeros?

A It generates a maximum length sequence

B It resets automatically

C It generates random numbers

D It stays at zero and produces no sequence

An all-zero seed causes the LFSR to remain stuck at zero, producing no sequence.

In a 4-bit LFSR, which of these could be valid taps for feedback?

A Bits 4 and 3

B Bits 1 and 2

C Bits 2 and 2

D Bits 5 and 6

Taps must be valid bit positions within the register size. For 4-bit, bits 4 and 3 are valid taps.

What is the main use of an LFSR in hardware design?

A To generate pseudo-random sequences

B To store large data

C To perform arithmetic operations

D To control power supply

LFSRs are mainly used to generate pseudo-random sequences for testing and cryptography.

In Verilog, how do you shift bits to the left and insert a new bit at the right end?

A Using register << 1

B Using {register[2:0], new_bit}

C Using {new_bit, register[3:1]}

D Using register >> 1

Concatenation {register[2:0], new_bit} shifts bits left and inserts new_bit at the right.

Explain how an LFSR generates a pseudo-random sequence and the role of taps in this process.

Think about how bits move and how feedback is calculated.

Describe how you would implement a 4-bit LFSR in Verilog including reset and clock signals.

Focus on the always block and how the register updates each clock cycle.

Practice

1.

What is the main purpose of a Linear Feedback Shift Register (LFSR) in digital circuits?

easy

A. To store large amounts of data

B. To perform arithmetic addition

C. To convert analog signals to digital

D. To generate a pseudo-random sequence of bits

Solution

1. Step 1: Understand LFSR function

   An LFSR uses shift and XOR feedback to produce a sequence of bits that appears random.

2. Step 2: Identify main use

   This sequence is used for pseudo-random number generation and testing, not arithmetic or storage.

3. Final Answer:

   To generate a pseudo-random sequence of bits -> Option D

4. Quick Check:

   LFSR = pseudo-random bit generator [OK]

Hint: LFSR creates random-like bits by shifting and XOR [OK]

Common Mistakes:

• Confusing LFSR with memory storage
• Thinking LFSR does arithmetic
• Assuming LFSR converts analog signals

2.

Which of the following is the correct Verilog syntax to declare a 4-bit register named lfsr?

easy

A. reg [3:0] lfsr;

B. reg lfsr[3:0];

C. wire [4:1] lfsr;

D. reg (3:0) lfsr;

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg [msb:lsb] name; syntax.

2. Step 2: Check each option

   reg [3:0] lfsr; uses correct syntax reg [3:0] lfsr;. reg lfsr[3:0]; uses wrong array style. wire [4:1] lfsr; uses wire, not reg. reg (3:0) lfsr; has invalid parentheses.

3. Final Answer:

   reg [3:0] lfsr; -> Option A

4. Quick Check:

   Correct reg syntax = reg [3:0] lfsr; [OK]

Hint: Use reg [msb:lsb] name; to declare registers [OK]

Common Mistakes:

• Using wire instead of reg for registers
• Incorrect bit range order or syntax
• Using parentheses instead of brackets

3.

Given this Verilog snippet for a 3-bit LFSR with taps at bits 3 and 2:

reg [2:0] lfsr = 3'b001;
always @(posedge clk) begin
  lfsr <= {lfsr[1:0], lfsr[2] ^ lfsr[1]};
end

What is the value of lfsr after 1 clock cycle?

medium

A. 3'b011

B. 3'b010

C. 3'b110

D. 3'b100

Solution

1. Step 1: Calculate first clock cycle

   Initial lfsr = 001. Feedback = lfsr[2]^lfsr[1] = 0^0=0.
   New lfsr = {lfsr[1:0], feedback} = {0,1,0} = 010.

2. Step 2: Confirm value

   After 1 clock cycle, lfsr = 3'b010, which matches 3'b010.

3. Final Answer:

   3'b010 -> Option B

4. Quick Check:

   Shift and XOR feedback = 010 after 1 cycle [OK]

Hint: Track bits step-by-step for each clock cycle [OK]

Common Mistakes:

• Mixing bit order in concatenation
• Calculating feedback incorrectly
• Confusing initial and next states

4.

Identify the error in this Verilog LFSR code snippet:

reg [3:0] lfsr = 4'b0000;
always @(posedge clk) begin
  lfsr <= {lfsr[2:0], lfsr[3] ^ lfsr[0]};
end

medium

A. The register size declaration is wrong

B. The feedback XOR taps are incorrect for 4-bit LFSR

C. Initial value can't be all zeros in LFSR

D. The concatenation order is reversed

Solution

1. Step 1: Check initial value

   LFSRs must not start with all zeros because they will stay stuck at zero forever (no feedback).

2. Step 2: Verify other parts

   Feedback taps and concatenation are valid for a 4-bit LFSR. Register size is correctly declared as 4 bits.

3. Final Answer:

   Initial value can't be all zeros in LFSR -> Option C

4. Quick Check:

   All-zero start = stuck LFSR [OK]

Hint: Never start LFSR with all zeros [OK]

Common Mistakes:

• Using zero initial value
• Misunderstanding feedback tap positions
• Incorrect bit concatenation order

5.

You want to design an 8-bit LFSR in Verilog that cycles through all 255 non-zero states before repeating. Which of the following tap combinations is a valid maximal-length feedback polynomial?

hard

A. Taps at bits 8 and 5 (lfsr[7] and lfsr[4])

B. Taps at bits 8 and 7 (lfsr[7] and lfsr[6])

C. Taps at bits 8 and 6 (lfsr[7] and lfsr[5])

D. Taps at bits 8 and 4 (lfsr[7] and lfsr[3])

Solution

1. Step 1: Recall maximal-length tap sets for 8-bit LFSR

   Common maximal-length taps for 8-bit LFSR are bits 8 and 5 (1-based indexing).

2. Step 2: Match options with known polynomials

   Taps at bits 8 and 5 (lfsr[7] and lfsr[4]) matches a valid maximal-length set. Taps at bits 8 and 7 (lfsr[7] and lfsr[6]), 8 and 6 (lfsr[7] and lfsr[5]), and 8 and 4 (lfsr[7] and lfsr[3]) are not maximal-length taps.

3. Step 3: Check indexing in Verilog (0-based)

   Bits 8 and 5 correspond to lfsr[7] and lfsr[4], which is Taps at bits 8 and 5 (lfsr[7] and lfsr[4]).

4. Final Answer:

   Taps at bits 8 and 5 (lfsr[7] and lfsr[4]) -> Option A

5. Quick Check:

   Maximal taps for 8-bit LFSR = bits 8 and 5 [OK]

Hint: Use known maximal taps like bits 8 and 5 for full cycle [OK]

Common Mistakes:

• Choosing non-maximal tap positions
• Confusing bit indexing (1-based vs 0-based)
• Assuming any two taps produce maximal length