Linear Feedback Shift Register (LFSR) in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Linear Feedback Shift Register (LFSR)?

An LFSR is a shift register where the input bit is a linear function (usually XOR) of its previous state bits. It generates pseudo-random sequences used in testing and cryptography.

beginner

How does feedback work in an LFSR?

Feedback is created by XORing selected bits (called taps) of the register and feeding the result back into the input bit of the shift register.

intermediate

What is the role of 'taps' in an LFSR?

Taps are specific bit positions in the register used to calculate the feedback bit by XOR operation. The choice of taps affects the sequence length and randomness.

intermediate

Write a simple Verilog code snippet for a 4-bit LFSR with taps at bits 4 and 3.

module lfsr_4bit(clk, reset, out); input clk, reset; output reg [3:0] out; wire feedback = out[3] ^ out[2]; always @(posedge clk or posedge reset) begin if (reset) out <= 4'b0001; else out <= {out[2:0], feedback}; end endmodule

beginner

Why is the initial value (seed) important in an LFSR?

The seed sets the starting state of the LFSR. If it is zero, the LFSR will stay at zero and not generate a sequence. A non-zero seed ensures the LFSR cycles through states.

What operation is commonly used to generate the feedback bit in an LFSR?

A OR

B AND

C XOR

D NOT

The feedback bit in an LFSR is typically generated by XORing selected bits (taps) of the register.

What happens if the initial seed of an LFSR is all zeros?

A It generates a maximum length sequence

B It resets automatically

C It generates random numbers

D It stays at zero and produces no sequence

An all-zero seed causes the LFSR to remain stuck at zero, producing no sequence.

In a 4-bit LFSR, which of these could be valid taps for feedback?

A Bits 4 and 3

B Bits 1 and 2

C Bits 2 and 2

D Bits 5 and 6

Taps must be valid bit positions within the register size. For 4-bit, bits 4 and 3 are valid taps.

What is the main use of an LFSR in hardware design?

A To generate pseudo-random sequences

B To store large data

C To perform arithmetic operations

D To control power supply

LFSRs are mainly used to generate pseudo-random sequences for testing and cryptography.

In Verilog, how do you shift bits to the left and insert a new bit at the right end?

A Using register << 1

B Using {register[2:0], new_bit}

C Using {new_bit, register[3:1]}

D Using register >> 1

Concatenation {register[2:0], new_bit} shifts bits left and inserts new_bit at the right.

Explain how an LFSR generates a pseudo-random sequence and the role of taps in this process.

Think about how bits move and how feedback is calculated.

Describe how you would implement a 4-bit LFSR in Verilog including reset and clock signals.

Focus on the always block and how the register updates each clock cycle.