Linear Feedback Shift Register (LFSR) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register named 'lfsr'.

Verilog

reg [3:0] [1] ;

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Alfsr

Bcount

Cdata

Dtemp

Attempts:

3 left

💡 Hint

Common Mistakes

Using unrelated names like 'data' or 'count'.

The register is named 'lfsr' to hold the shift register bits.

2fill in blank

medium

Complete the code to assign the feedback bit as XOR of bits 3 and 2 of the LFSR.

Verilog

wire feedback = lfsr[3] [1] lfsr[2];

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A&

B^

C|

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Using AND (&) or OR (|) instead of XOR.

The feedback bit is the XOR (^) of bits 3 and 2.

3fill in blank

hard

Fix the error in the always block sensitivity list to trigger on the positive edge of clock.

Verilog

always @([1]) begin
  if (reset) lfsr <= 4'b0001;
  else lfsr <= {lfsr[2:0], feedback};
end

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Aposedge clk

Bnegedge clk

Cclk

Dposedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'negedge clk' or just 'clk' without edge specification.

The always block should trigger on the positive edge of the clock signal.

4fill in blank

hard

Fill both blanks to complete the LFSR update logic inside the always block.

Verilog

if (reset) lfsr <= [1];
else lfsr <= [2];

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A4'b0001

B{lfsr[2:0], feedback}

C4'b1111

D{feedback, lfsr[3:1]}

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong reset value or shifting direction.

On reset, LFSR is initialized to 0001. Otherwise, it shifts left with feedback bit appended.

5fill in blank

hard

Fill all three blanks to create a module named 'lfsr4' with inputs clk, reset and output lfsr_out.

Verilog

module [1](
  input wire [2],
  input wire reset,
  output reg [3:0] [3]
);

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Alfsr4

Bclk

Clfsr_out

Dclock

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clock' instead of 'clk' or wrong output name.

The module is named 'lfsr4'. The clock input is 'clk'. The output register is 'lfsr_out'.