JK flip-flop behavior in Verilog - Step-by-Step Execution

Concept Flow - JK flip-flop behavior

Inputs: J, K, Clock, Q

↓

On Clock Rising Edge

↓

Check J and K values

↓

Hold Q

↓

J=1,K=1?

Yes↓

Toggle Q

↓

Output Q

The JK flip-flop updates output Q on the clock's rising edge based on inputs J and K: hold, reset, set, or toggle.

Execution Sample

Verilog

always @(posedge clk) begin
  case ({J, K})
    2'b00: Q <= Q;       // Hold
    2'b01: Q <= 0;       // Reset
    2'b10: Q <= 1;       // Set
    2'b11: Q <= ~Q;      // Toggle
  endcase
end

This code updates Q on clock rising edge according to JK inputs.

Execution Table

Step	J	K	Clock Edge	Previous Q	Condition	Action	New Q
1	0	0	Rising	0	J=0,K=0	Hold Q	0
2	0	1	Rising	0	J=0,K=1	Reset Q=0	0
3	1	0	Rising	0	J=1,K=0	Set Q=1	1
4	1	1	Rising	1	J=1,K=1	Toggle Q	0
5	1	1	Rising	0	J=1,K=1	Toggle Q	1
6	0	0	Rising	1	J=0,K=0	Hold Q	1
7	0	1	Rising	1	J=0,K=1	Reset Q=0	0
Exit	-	-	-	-	No more clock edges	Stop	-

💡 No more clock rising edges to trigger state changes.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	Final
Q	0	0	0	1	0	1	1	0	0

Key Moments - 3 Insights

Why does Q not change when J=0 and K=0?

When J=0 and K=0 (see Step 1 and Step 6 in execution_table), the flip-flop holds its previous state, so Q remains unchanged.

What happens when both J and K are 1?

When J=1 and K=1 (see Steps 4 and 5), the flip-flop toggles Q, flipping it from 1 to 0 or 0 to 1.

Why does Q reset to 0 when J=0 and K=1?

At Steps 2 and 7, J=0 and K=1 causes Q to reset to 0, regardless of previous Q.

Visual Quiz - 3 Questions

Look at the execution_table at Step 3. What is the new value of Q?

A 0

B Toggle previous Q

C 1

D Hold previous Q

💡 Hint

Check the 'New Q' column at Step 3 where J=1 and K=0 sets Q to 1.

At which step does the flip-flop toggle Q from 1 to 0?

A Step 4

B Step 2

C Step 5

D Step 7

💡 Hint

Look at Step 4 in execution_table where J=1 and K=1 and previous Q=1.

If J=0 and K=0 at Step 6, what happens to Q?

A Q resets to 0

B Q holds previous value

C Q sets to 1

D Q toggles

💡 Hint

Refer to Step 6 in execution_table where J=0,K=0 causes hold action.

Concept Snapshot

JK Flip-Flop Behavior:
- Triggered on clock rising edge
- J=0,K=0: Hold Q
- J=0,K=1: Reset Q=0
- J=1,K=0: Set Q=1
- J=1,K=1: Toggle Q
- Used for memory and toggle operations

Full Transcript

This visual trace shows how a JK flip-flop updates its output Q on each rising clock edge based on inputs J and K. When both J and K are 0, Q holds its previous value. When J=0 and K=1, Q resets to 0. When J=1 and K=0, Q sets to 1. When both J and K are 1, Q toggles its value. The execution table steps through these cases with example inputs and shows how Q changes. The variable tracker follows Q's value after each step. Key moments clarify common confusions about hold, reset, and toggle behaviors. The quiz questions test understanding of Q's changes at specific steps. This helps beginners see exactly how JK flip-flop logic works in practice.

Practice

1. What is the output behavior of a JK flip-flop when both inputs J and K are 0?

easy

A. The output toggles its state.

B. The output resets to 0.

C. The output sets to 1.

D. The output holds its previous state.

Solution

1. Step 1: Understand JK flip-flop input conditions

   When both J and K are 0, the flip-flop does not change its output.

2. Step 2: Recall JK flip-flop behavior for J=0 and K=0

   The output remains the same as the previous state, meaning it holds its value.

3. Final Answer:

   The output holds its previous state. -> Option D

4. Quick Check:

   J=0, K=0 means hold state [OK]

Hint: J=0 and K=0 means no change, output holds [OK]

Common Mistakes:

• Confusing hold with reset or set
• Thinking output toggles when inputs are zero
• Assuming output always resets on zero inputs

2. Which of the following is the correct Verilog sensitivity list for a JK flip-flop triggered on the rising edge of clock clk?

easy

A. always @(posedge clk or posedge reset)

B. always @(posedge clk)

C. always @(clk)

D. always @(negedge clk)

Solution

1. Step 1: Identify clock edge triggering

   JK flip-flops are usually triggered on the rising edge of the clock signal.

2. Step 2: Choose correct sensitivity list syntax

   In Verilog, rising edge is specified by posedge clk, so always @(posedge clk) is correct.

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge clk [OK]

Hint: posedge clk means rising edge trigger [OK]

Common Mistakes:

• Using negedge instead of posedge
• Missing edge keyword in sensitivity list
• Including unrelated signals without reason

3. Given the following Verilog code snippet for a JK flip-flop, what will be the output q after the clock rising edge if j=1, k=0, and previous q=0?

always @(posedge clk) begin
  case ({j,k})
    2'b00: q <= q;
    2'b01: q <= 0;
    2'b10: q <= 1;
    2'b11: q <= ~q;
  endcase
end

medium

A. 1

B. Toggle previous q

C. 0

D. No change

Solution

1. Step 1: Identify input combination and previous output

   Inputs are j=1, k=0, previous q=0.

2. Step 2: Match input to case statement

   For {j,k} = 2'b10, the code sets q to 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   J=1, K=0 sets q=1 [OK]

Hint: J=1 and K=0 sets output to 1 [OK]

Common Mistakes:

• Confusing toggle with set
• Ignoring previous q value
• Misreading case statement

4. Identify the error in this JK flip-flop Verilog code snippet:

always @(posedge clk) begin
  if (j == 1 && k == 1)
    q <= q;
  else if (j == 1)
    q <= 1;
  else if (k == 1)
    q <= 0;
end

medium

A. Missing sensitivity to reset signal.

B. Incorrect use of non-blocking assignment '<='.

C. The toggle condition is incorrect; it should invert q, not hold it.

D. The if-else structure is missing an else case for j=0 and k=0.

Solution

1. Step 1: Analyze toggle condition for j=1 and k=1

   The code holds q when both j and k are 1, but JK flip-flop should toggle q in this case.

2. Step 2: Verify other conditions and assignments

   Other conditions set or reset q correctly, but toggle logic is wrong.

3. Final Answer:

   The toggle condition is incorrect; it should invert q, not hold it. -> Option C

4. Quick Check:

   J=1 and K=1 toggles q, not holds [OK]

Hint: J=K=1 means toggle output, not hold [OK]

Common Mistakes:

• Assuming hold on J=K=1 instead of toggle
• Ignoring toggle logic in JK flip-flop
• Confusing blocking and non-blocking assignments

5. You want to design a JK flip-flop in Verilog that asynchronously resets q to 0 when reset is high, otherwise behaves normally on the rising edge of clk. Which code snippet correctly implements this behavior?

hard

A. always @(posedge clk or posedge reset) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

B. always @(posedge clk) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

C. always @(posedge reset or posedge clk) begin\n if (reset) q <= 1;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

D. always @(posedge clk or negedge reset) begin\n if (!reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

Solution

1. Step 1: Identify asynchronous reset sensitivity

   The reset is asynchronous, so it must be in the sensitivity list with posedge reset.

2. Step 2: Check reset behavior and JK logic

   When reset is high, q is set to 0 immediately. Otherwise, JK flip-flop behavior is implemented correctly with case statement.

3. Final Answer:

   Code with sensitivity list @(posedge clk or posedge reset) and reset logic first. -> Option A

4. Quick Check:

   Asynchronous reset uses posedge reset in sensitivity list [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Placing reset only inside clock edge sensitivity
• Setting q to 1 on reset instead of 0
• Using negedge reset incorrectly for active-high reset