JK flip-flop behavior in Verilog - Step-by-Step Execution

Concept Flow - JK flip-flop behavior

Inputs: J, K, Clock, Q

↓

On Clock Rising Edge

↓

Check J and K values

↓

Hold Q

↓

J=1,K=1?

Yes↓

Toggle Q

↓

Output Q

The JK flip-flop updates output Q on the clock's rising edge based on inputs J and K: hold, reset, set, or toggle.

Execution Sample

Verilog

always @(posedge clk) begin
  case ({J, K})
    2'b00: Q <= Q;       // Hold
    2'b01: Q <= 0;       // Reset
    2'b10: Q <= 1;       // Set
    2'b11: Q <= ~Q;      // Toggle
  endcase
end

This code updates Q on clock rising edge according to JK inputs.

Execution Table

Step	J	K	Clock Edge	Previous Q	Condition	Action	New Q
1	0	0	Rising	0	J=0,K=0	Hold Q	0
2	0	1	Rising	0	J=0,K=1	Reset Q=0	0
3	1	0	Rising	0	J=1,K=0	Set Q=1	1
4	1	1	Rising	1	J=1,K=1	Toggle Q	0
5	1	1	Rising	0	J=1,K=1	Toggle Q	1
6	0	0	Rising	1	J=0,K=0	Hold Q	1
7	0	1	Rising	1	J=0,K=1	Reset Q=0	0
Exit	-	-	-	-	No more clock edges	Stop	-

💡 No more clock rising edges to trigger state changes.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	Final
Q	0	0	0	1	0	1	1	0	0

Key Moments - 3 Insights

Why does Q not change when J=0 and K=0?

When J=0 and K=0 (see Step 1 and Step 6 in execution_table), the flip-flop holds its previous state, so Q remains unchanged.

What happens when both J and K are 1?

When J=1 and K=1 (see Steps 4 and 5), the flip-flop toggles Q, flipping it from 1 to 0 or 0 to 1.

Why does Q reset to 0 when J=0 and K=1?

At Steps 2 and 7, J=0 and K=1 causes Q to reset to 0, regardless of previous Q.

Visual Quiz - 3 Questions

Look at the execution_table at Step 3. What is the new value of Q?

A 0

B Toggle previous Q

C 1

D Hold previous Q

💡 Hint

Check the 'New Q' column at Step 3 where J=1 and K=0 sets Q to 1.

At which step does the flip-flop toggle Q from 1 to 0?

A Step 4

B Step 2

C Step 5

D Step 7

💡 Hint

Look at Step 4 in execution_table where J=1 and K=1 and previous Q=1.

If J=0 and K=0 at Step 6, what happens to Q?

A Q resets to 0

B Q holds previous value

C Q sets to 1

D Q toggles

💡 Hint

Refer to Step 6 in execution_table where J=0,K=0 causes hold action.

Concept Snapshot

JK Flip-Flop Behavior:
- Triggered on clock rising edge
- J=0,K=0: Hold Q
- J=0,K=1: Reset Q=0
- J=1,K=0: Set Q=1
- J=1,K=1: Toggle Q
- Used for memory and toggle operations

Full Transcript

This visual trace shows how a JK flip-flop updates its output Q on each rising clock edge based on inputs J and K. When both J and K are 0, Q holds its previous value. When J=0 and K=1, Q resets to 0. When J=1 and K=0, Q sets to 1. When both J and K are 1, Q toggles its value. The execution table steps through these cases with example inputs and shows how Q changes. The variable tracker follows Q's value after each step. Key moments clarify common confusions about hold, reset, and toggle behaviors. The quiz questions test understanding of Q's changes at specific steps. This helps beginners see exactly how JK flip-flop logic works in practice.