JK flip-flop behavior in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a JK flip-flop?

A JK flip-flop is a digital memory circuit that can store one bit of data. It has two inputs, J and K, and changes its output based on these inputs and the clock signal.

beginner

What happens when J=0 and K=0 in a JK flip-flop?

When J=0 and K=0, the JK flip-flop keeps its previous state. It does not change the output.

intermediate

Describe the toggle behavior of a JK flip-flop.

When both J=1 and K=1, the JK flip-flop toggles its output. If the output was 0, it becomes 1; if it was 1, it becomes 0.

intermediate

Write the Verilog sensitivity list for a JK flip-flop triggered on the rising edge of the clock.

The sensitivity list is: always @(posedge clk) which means the block runs when the clock signal rises from 0 to 1.

beginner

What is the output Q after a clock pulse if J=1, K=0 and the previous Q was 0?

If J=1 and K=0, the JK flip-flop sets Q to 1 on the clock pulse, so the output changes from 0 to 1.

In a JK flip-flop, what does the input combination J=0 and K=1 do on a clock pulse?

A Resets the output to 0

B Sets the output to 1

C Toggles the output

D No change to output

When J=0 and K=1, the JK flip-flop resets the output Q to 0 on the clock pulse.

What is the output behavior when J=1 and K=1 in a JK flip-flop?

A Output is set to 1

B Output is reset to 0

C Output remains unchanged

D Output toggles

When both J and K are 1, the JK flip-flop toggles its output on the clock edge.

Which Verilog keyword is used to describe a block sensitive to the rising edge of a clock?

A posedge

B negedge

C always

D initial

The keyword 'posedge' is used to trigger on the rising edge of a signal like a clock.

If the previous output Q=1 and inputs J=0, K=0, what will be the output after the clock pulse?

A 0

B Toggle to 0

C 1

D Undefined

With J=0 and K=0, the JK flip-flop holds its previous state, so output remains 1.

What is the main advantage of a JK flip-flop over an SR flip-flop?

A It uses fewer gates

B It has no invalid input state

C It is asynchronous

D It cannot toggle

The JK flip-flop eliminates the invalid state present in SR flip-flops by toggling when both inputs are 1.

Explain how a JK flip-flop changes its output based on different input combinations.

Think about each input pair and what the flip-flop does on the clock edge.

Describe how you would write a Verilog always block to model a JK flip-flop triggered on the rising edge of a clock.

Focus on the sensitivity list and conditional logic inside the block.

Practice

1. What is the output behavior of a JK flip-flop when both inputs J and K are 0?

easy

A. The output toggles its state.

B. The output resets to 0.

C. The output sets to 1.

D. The output holds its previous state.

Solution

1. Step 1: Understand JK flip-flop input conditions

   When both J and K are 0, the flip-flop does not change its output.

2. Step 2: Recall JK flip-flop behavior for J=0 and K=0

   The output remains the same as the previous state, meaning it holds its value.

3. Final Answer:

   The output holds its previous state. -> Option D

4. Quick Check:

   J=0, K=0 means hold state [OK]

Hint: J=0 and K=0 means no change, output holds [OK]

Common Mistakes:

• Confusing hold with reset or set
• Thinking output toggles when inputs are zero
• Assuming output always resets on zero inputs

2. Which of the following is the correct Verilog sensitivity list for a JK flip-flop triggered on the rising edge of clock clk?

easy

A. always @(posedge clk or posedge reset)

B. always @(posedge clk)

C. always @(clk)

D. always @(negedge clk)

Solution

1. Step 1: Identify clock edge triggering

   JK flip-flops are usually triggered on the rising edge of the clock signal.

2. Step 2: Choose correct sensitivity list syntax

   In Verilog, rising edge is specified by posedge clk, so always @(posedge clk) is correct.

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge clk [OK]

Hint: posedge clk means rising edge trigger [OK]

Common Mistakes:

• Using negedge instead of posedge
• Missing edge keyword in sensitivity list
• Including unrelated signals without reason

3. Given the following Verilog code snippet for a JK flip-flop, what will be the output q after the clock rising edge if j=1, k=0, and previous q=0?

always @(posedge clk) begin
  case ({j,k})
    2'b00: q <= q;
    2'b01: q <= 0;
    2'b10: q <= 1;
    2'b11: q <= ~q;
  endcase
end

medium

A. 1

B. Toggle previous q

C. 0

D. No change

Solution

1. Step 1: Identify input combination and previous output

   Inputs are j=1, k=0, previous q=0.

2. Step 2: Match input to case statement

   For {j,k} = 2'b10, the code sets q to 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   J=1, K=0 sets q=1 [OK]

Hint: J=1 and K=0 sets output to 1 [OK]

Common Mistakes:

• Confusing toggle with set
• Ignoring previous q value
• Misreading case statement

4. Identify the error in this JK flip-flop Verilog code snippet:

always @(posedge clk) begin
  if (j == 1 && k == 1)
    q <= q;
  else if (j == 1)
    q <= 1;
  else if (k == 1)
    q <= 0;
end

medium

A. Missing sensitivity to reset signal.

B. Incorrect use of non-blocking assignment '<='.

C. The toggle condition is incorrect; it should invert q, not hold it.

D. The if-else structure is missing an else case for j=0 and k=0.

Solution

1. Step 1: Analyze toggle condition for j=1 and k=1

   The code holds q when both j and k are 1, but JK flip-flop should toggle q in this case.

2. Step 2: Verify other conditions and assignments

   Other conditions set or reset q correctly, but toggle logic is wrong.

3. Final Answer:

   The toggle condition is incorrect; it should invert q, not hold it. -> Option C

4. Quick Check:

   J=1 and K=1 toggles q, not holds [OK]

Hint: J=K=1 means toggle output, not hold [OK]

Common Mistakes:

• Assuming hold on J=K=1 instead of toggle
• Ignoring toggle logic in JK flip-flop
• Confusing blocking and non-blocking assignments

5. You want to design a JK flip-flop in Verilog that asynchronously resets q to 0 when reset is high, otherwise behaves normally on the rising edge of clk. Which code snippet correctly implements this behavior?

hard

A. always @(posedge clk or posedge reset) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

B. always @(posedge clk) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

C. always @(posedge reset or posedge clk) begin\n if (reset) q <= 1;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

D. always @(posedge clk or negedge reset) begin\n if (!reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

Solution

1. Step 1: Identify asynchronous reset sensitivity

   The reset is asynchronous, so it must be in the sensitivity list with posedge reset.

2. Step 2: Check reset behavior and JK logic

   When reset is high, q is set to 0 immediately. Otherwise, JK flip-flop behavior is implemented correctly with case statement.

3. Final Answer:

   Code with sensitivity list @(posedge clk or posedge reset) and reset logic first. -> Option A

4. Quick Check:

   Asynchronous reset uses posedge reset in sensitivity list [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Placing reset only inside clock edge sensitivity
• Setting q to 1 on reset instead of 0
• Using negedge reset incorrectly for active-high reset