JK flip-flop behavior in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a JK flip-flop?

A JK flip-flop is a digital memory circuit that can store one bit of data. It has two inputs, J and K, and changes its output based on these inputs and the clock signal.

beginner

What happens when J=0 and K=0 in a JK flip-flop?

When J=0 and K=0, the JK flip-flop keeps its previous state. It does not change the output.

intermediate

Describe the toggle behavior of a JK flip-flop.

When both J=1 and K=1, the JK flip-flop toggles its output. If the output was 0, it becomes 1; if it was 1, it becomes 0.

intermediate

Write the Verilog sensitivity list for a JK flip-flop triggered on the rising edge of the clock.

The sensitivity list is: always @(posedge clk) which means the block runs when the clock signal rises from 0 to 1.

beginner

What is the output Q after a clock pulse if J=1, K=0 and the previous Q was 0?

If J=1 and K=0, the JK flip-flop sets Q to 1 on the clock pulse, so the output changes from 0 to 1.

In a JK flip-flop, what does the input combination J=0 and K=1 do on a clock pulse?

A Resets the output to 0

B Sets the output to 1

C Toggles the output

D No change to output

When J=0 and K=1, the JK flip-flop resets the output Q to 0 on the clock pulse.

What is the output behavior when J=1 and K=1 in a JK flip-flop?

A Output is set to 1

B Output is reset to 0

C Output remains unchanged

D Output toggles

When both J and K are 1, the JK flip-flop toggles its output on the clock edge.

Which Verilog keyword is used to describe a block sensitive to the rising edge of a clock?

A posedge

B negedge

C always

D initial

The keyword 'posedge' is used to trigger on the rising edge of a signal like a clock.

If the previous output Q=1 and inputs J=0, K=0, what will be the output after the clock pulse?

A 0

B Toggle to 0

C 1

D Undefined

With J=0 and K=0, the JK flip-flop holds its previous state, so output remains 1.

What is the main advantage of a JK flip-flop over an SR flip-flop?

A It uses fewer gates

B It has no invalid input state

C It is asynchronous

D It cannot toggle

The JK flip-flop eliminates the invalid state present in SR flip-flops by toggling when both inputs are 1.

Explain how a JK flip-flop changes its output based on different input combinations.

Think about each input pair and what the flip-flop does on the clock edge.

Describe how you would write a Verilog always block to model a JK flip-flop triggered on the rising edge of a clock.

Focus on the sensitivity list and conditional logic inside the block.