JK flip-flop behavior in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of JK Flip-Flop with J=1, K=0

Given the following Verilog code for a JK flip-flop, what is the output Q after the rising edge of the clock if J=1, K=0 and initial Q=0?

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    case ({J,K})
      2'b00: Q <= Q;
      2'b01: Q <= 0;
      2'b10: Q <= 1;
      2'b11: Q <= ~Q;
    endcase
  end
endmodule

A Q = 1

B Q = 0

C Q remains undefined

D Q toggles to 1 then back to 0

💡 Hint

Remember that J=1 and K=0 sets the flip-flop output to 1 on the clock edge.

When J=1 and K=0, the JK flip-flop sets Q to 1 at the rising clock edge regardless of previous Q.

❓ Predict Output

intermediate

JK Flip-Flop Output with J=1, K=1

What will be the output Q after the rising edge of the clock if J=1, K=1 and initial Q=0 in the JK flip-flop below?

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    case ({J,K})
      2'b00: Q <= Q;
      2'b01: Q <= 0;
      2'b10: Q <= 1;
      2'b11: Q <= ~Q;
    endcase
  end
endmodule

A Q toggles to 1

B Q = 1

C Q = 0

D Q toggles to 1 then back to 0

💡 Hint

When both J and K are 1, the JK flip-flop toggles the output.

With J=1 and K=1, the flip-flop toggles Q from 0 to 1 at the clock edge.

🔧 Debug

advanced

Identify the error in JK Flip-Flop code

What error will this Verilog JK flip-flop code produce when compiled?

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    if (J == 1 && K == 1)
      Q = ~Q;
    else if (J == 1 && K == 0)
      Q = 1;
    else if (J == 0 && K == 1)
      Q = 0;
    else
      Q = Q;
  end
endmodule

A Syntax error: missing semicolon after Q = ~Q

B Runtime error: Q is not initialized

C No error, code compiles and works correctly

D Warning: blocking assignments used in sequential always block

💡 Hint

Consider the difference between blocking (=) and non-blocking (<=) assignments in sequential logic.

Using blocking assignments (=) inside an always @(posedge clk) block can cause simulation mismatches and is discouraged; non-blocking (<=) should be used.

🧠 Conceptual

advanced

JK Flip-Flop Behavior on Inputs J=0, K=0

What is the behavior of a JK flip-flop when both inputs J and K are 0 at the rising edge of the clock?

A The output Q resets to 0

B The output Q holds its previous state

C The output Q toggles

D The output Q sets to 1

💡 Hint

Think about what happens when no input commands a change.

When J=0 and K=0, the JK flip-flop holds its current output value without change.

❓ Predict Output

expert

Final Q value after multiple clock cycles

Given the JK flip-flop module below and the input sequence on J and K over 4 clock cycles, what is the final value of Q? Initial Q=0. Clock cycles inputs: Cycle 1: J=1, K=0 Cycle 2: J=1, K=1 Cycle 3: J=0, K=1 Cycle 4: J=0, K=0

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    case ({J,K})
      2'b00: Q <= Q;
      2'b01: Q <= 0;
      2'b10: Q <= 1;
      2'b11: Q <= ~Q;
    endcase
  end
endmodule

A Q toggled twice, final Q = 1

B Q = 1

C Q = 0

D Q toggled twice, final Q = 0

💡 Hint

Trace the output Q step-by-step through each clock cycle.

Cycle 1 sets Q=1; Cycle 2 toggles Q to 0; Cycle 3 resets Q to 0; Cycle 4 holds Q=0; final Q=0.

Practice

1. What is the output behavior of a JK flip-flop when both inputs J and K are 0?

easy

A. The output toggles its state.

B. The output resets to 0.

C. The output sets to 1.

D. The output holds its previous state.

Solution

1. Step 1: Understand JK flip-flop input conditions

   When both J and K are 0, the flip-flop does not change its output.

2. Step 2: Recall JK flip-flop behavior for J=0 and K=0

   The output remains the same as the previous state, meaning it holds its value.

3. Final Answer:

   The output holds its previous state. -> Option D

4. Quick Check:

   J=0, K=0 means hold state [OK]

Hint: J=0 and K=0 means no change, output holds [OK]

Common Mistakes:

• Confusing hold with reset or set
• Thinking output toggles when inputs are zero
• Assuming output always resets on zero inputs

2. Which of the following is the correct Verilog sensitivity list for a JK flip-flop triggered on the rising edge of clock clk?

easy

A. always @(posedge clk or posedge reset)

B. always @(posedge clk)

C. always @(clk)

D. always @(negedge clk)

Solution

1. Step 1: Identify clock edge triggering

   JK flip-flops are usually triggered on the rising edge of the clock signal.

2. Step 2: Choose correct sensitivity list syntax

   In Verilog, rising edge is specified by posedge clk, so always @(posedge clk) is correct.

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge clk [OK]

Hint: posedge clk means rising edge trigger [OK]

Common Mistakes:

• Using negedge instead of posedge
• Missing edge keyword in sensitivity list
• Including unrelated signals without reason

3. Given the following Verilog code snippet for a JK flip-flop, what will be the output q after the clock rising edge if j=1, k=0, and previous q=0?

always @(posedge clk) begin
  case ({j,k})
    2'b00: q <= q;
    2'b01: q <= 0;
    2'b10: q <= 1;
    2'b11: q <= ~q;
  endcase
end

medium

A. 1

B. Toggle previous q

C. 0

D. No change

Solution

1. Step 1: Identify input combination and previous output

   Inputs are j=1, k=0, previous q=0.

2. Step 2: Match input to case statement

   For {j,k} = 2'b10, the code sets q to 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   J=1, K=0 sets q=1 [OK]

Hint: J=1 and K=0 sets output to 1 [OK]

Common Mistakes:

• Confusing toggle with set
• Ignoring previous q value
• Misreading case statement

4. Identify the error in this JK flip-flop Verilog code snippet:

always @(posedge clk) begin
  if (j == 1 && k == 1)
    q <= q;
  else if (j == 1)
    q <= 1;
  else if (k == 1)
    q <= 0;
end

medium

A. Missing sensitivity to reset signal.

B. Incorrect use of non-blocking assignment '<='.

C. The toggle condition is incorrect; it should invert q, not hold it.

D. The if-else structure is missing an else case for j=0 and k=0.

Solution

1. Step 1: Analyze toggle condition for j=1 and k=1

   The code holds q when both j and k are 1, but JK flip-flop should toggle q in this case.

2. Step 2: Verify other conditions and assignments

   Other conditions set or reset q correctly, but toggle logic is wrong.

3. Final Answer:

   The toggle condition is incorrect; it should invert q, not hold it. -> Option C

4. Quick Check:

   J=1 and K=1 toggles q, not holds [OK]

Hint: J=K=1 means toggle output, not hold [OK]

Common Mistakes:

• Assuming hold on J=K=1 instead of toggle
• Ignoring toggle logic in JK flip-flop
• Confusing blocking and non-blocking assignments

5. You want to design a JK flip-flop in Verilog that asynchronously resets q to 0 when reset is high, otherwise behaves normally on the rising edge of clk. Which code snippet correctly implements this behavior?

hard

A. always @(posedge clk or posedge reset) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

B. always @(posedge clk) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

C. always @(posedge reset or posedge clk) begin\n if (reset) q <= 1;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

D. always @(posedge clk or negedge reset) begin\n if (!reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

Solution

1. Step 1: Identify asynchronous reset sensitivity

   The reset is asynchronous, so it must be in the sensitivity list with posedge reset.

2. Step 2: Check reset behavior and JK logic

   When reset is high, q is set to 0 immediately. Otherwise, JK flip-flop behavior is implemented correctly with case statement.

3. Final Answer:

   Code with sensitivity list @(posedge clk or posedge reset) and reset logic first. -> Option A

4. Quick Check:

   Asynchronous reset uses posedge reset in sensitivity list [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Placing reset only inside clock edge sensitivity
• Setting q to 1 on reset instead of 0
• Using negedge reset incorrectly for active-high reset