JK flip-flop behavior in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of JK Flip-Flop with J=1, K=0

Given the following Verilog code for a JK flip-flop, what is the output Q after the rising edge of the clock if J=1, K=0 and initial Q=0?

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    case ({J,K})
      2'b00: Q <= Q;
      2'b01: Q <= 0;
      2'b10: Q <= 1;
      2'b11: Q <= ~Q;
    endcase
  end
endmodule

A Q = 1

B Q = 0

C Q remains undefined

D Q toggles to 1 then back to 0

💡 Hint

Remember that J=1 and K=0 sets the flip-flop output to 1 on the clock edge.

When J=1 and K=0, the JK flip-flop sets Q to 1 at the rising clock edge regardless of previous Q.

❓ Predict Output

intermediate

JK Flip-Flop Output with J=1, K=1

What will be the output Q after the rising edge of the clock if J=1, K=1 and initial Q=0 in the JK flip-flop below?

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    case ({J,K})
      2'b00: Q <= Q;
      2'b01: Q <= 0;
      2'b10: Q <= 1;
      2'b11: Q <= ~Q;
    endcase
  end
endmodule

A Q toggles to 1

B Q = 1

C Q = 0

D Q toggles to 1 then back to 0

💡 Hint

When both J and K are 1, the JK flip-flop toggles the output.

With J=1 and K=1, the flip-flop toggles Q from 0 to 1 at the clock edge.

🔧 Debug

advanced

Identify the error in JK Flip-Flop code

What error will this Verilog JK flip-flop code produce when compiled?

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    if (J == 1 && K == 1)
      Q = ~Q;
    else if (J == 1 && K == 0)
      Q = 1;
    else if (J == 0 && K == 1)
      Q = 0;
    else
      Q = Q;
  end
endmodule

A Syntax error: missing semicolon after Q = ~Q

B Runtime error: Q is not initialized

C No error, code compiles and works correctly

D Warning: blocking assignments used in sequential always block

💡 Hint

Consider the difference between blocking (=) and non-blocking (<=) assignments in sequential logic.

Using blocking assignments (=) inside an always @(posedge clk) block can cause simulation mismatches and is discouraged; non-blocking (<=) should be used.

🧠 Conceptual

advanced

JK Flip-Flop Behavior on Inputs J=0, K=0

What is the behavior of a JK flip-flop when both inputs J and K are 0 at the rising edge of the clock?

A The output Q resets to 0

B The output Q holds its previous state

C The output Q toggles

D The output Q sets to 1

💡 Hint

Think about what happens when no input commands a change.

When J=0 and K=0, the JK flip-flop holds its current output value without change.

❓ Predict Output

expert

Final Q value after multiple clock cycles

Given the JK flip-flop module below and the input sequence on J and K over 4 clock cycles, what is the final value of Q? Initial Q=0. Clock cycles inputs: Cycle 1: J=1, K=0 Cycle 2: J=1, K=1 Cycle 3: J=0, K=1 Cycle 4: J=0, K=0

Verilog

module jk_ff(input clk, input J, input K, output reg Q);
  always @(posedge clk) begin
    case ({J,K})
      2'b00: Q <= Q;
      2'b01: Q <= 0;
      2'b10: Q <= 1;
      2'b11: Q <= ~Q;
    endcase
  end
endmodule

A Q toggled twice, final Q = 1

B Q = 1

C Q = 0

D Q toggled twice, final Q = 0

💡 Hint

Trace the output Q step-by-step through each clock cycle.

Cycle 1 sets Q=1; Cycle 2 toggles Q to 0; Cycle 3 resets Q to 0; Cycle 4 holds Q=0; final Q=0.