JK flip-flop behavior in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the JK flip-flop module with inputs and outputs.

Verilog

module jk_ff(input clk, input [1], input j, input k, output reg q);

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Aclear

Brst

Cset

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset' instead of 'rst' which is inconsistent with the module naming.

The input is named rst to represent reset signal.

2fill in blank

medium

Complete the always block sensitivity list to trigger on the positive edge of clock and reset.

Verilog

always @(posedge clk or posedge [1]) begin

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Aj

Bk

Cq

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using data inputs like 'j' or 'k' in sensitivity list instead of reset.

The flip-flop reacts to the positive edge of the reset signal rst.

3fill in blank

hard

Fix the error in the reset condition to set output q to 0.

Verilog

if ([1]) q <= 0;

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Arst

Bclk

Cj

Dk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or data inputs instead of reset in the condition.

The reset condition checks if rst is high to clear q.

4fill in blank

hard

Fill both blanks to complete the JK flip-flop behavior inside the else block.

Verilog

else begin
  case([1], [2])
    2'b00: q <= q;
    2'b01: q <= 0;
    2'b10: q <= 1;
    2'b11: q <= ~q;
  endcase
end

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Aj

Bk

Cclk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset signals inside the case statement.

The JK flip-flop behavior depends on inputs j and k.

5fill in blank

hard

Fill all three blanks to complete the module end and output declaration.

Verilog

endmodule

assign [1] = q;

// Module [2] with inputs [3]

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Aq_out

Bjk_ff

Cclk, rst, j, k

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using internal signal q directly as output name.

Incorrect module name or input list.

The output is assigned to q_out. The module name is jk_ff with inputs clk, rst, j, k.