JK flip-flop behavior in Verilog - Mini Project: Build & Apply

JK Flip-Flop Behavior

📖 Scenario: You are designing a simple digital circuit that uses a JK flip-flop to store and toggle a bit based on input signals.

🎯 Goal: Build a Verilog module that models the behavior of a JK flip-flop with asynchronous reset and clock input.

📋 What You'll Learn

Create a Verilog module named jk_flip_flop with inputs J, K, clk, and reset.

Add an output Q that holds the flip-flop state.

Implement the JK flip-flop behavior inside an always block triggered on the rising edge of clk or when reset is high.

On reset, Q should be set to 0.

On clock edge, update Q according to JK flip-flop rules: if J=K=0, hold state; if J=0 and K=1, reset Q; if J=1 and K=0, set Q; if J=K=1, toggle Q.

💡 Why This Matters

🌍 Real World

JK flip-flops are basic building blocks in digital electronics used for memory storage, counters, and state machines.

💼 Career

Understanding flip-flop behavior is essential for hardware design engineers and FPGA developers working on digital circuits.

1

Create the JK flip-flop module and declare inputs and output

Write a Verilog module named jk_flip_flop with inputs J, K, clk, and reset. Declare an output Q as a reg type.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

// Your code here

endmodule

Need a hint?

Start by writing the module header with the exact input and output names and types.

2

Add an always block triggered on rising edge of clk or reset

Inside the jk_flip_flop module, add an always block triggered on the rising edge of clk or when reset is high.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

always @(posedge clk or posedge reset) begin
    // Your code here
end

endmodule

Need a hint?

Use always @(posedge clk or posedge reset) to detect clock and reset events.

3

Implement reset and JK flip-flop behavior inside the always block

Inside the always block, write an if statement to set Q = 0 when reset is high. Otherwise, implement JK flip-flop logic: if J == 0 and K == 0, keep Q unchanged; if J == 0 and K == 1, set Q = 0; if J == 1 and K == 0, set Q = 1; if J == 1 and K == 1, toggle Q.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Your code here
    end else begin
        // Your code here
    end
end

endmodule

Need a hint?

Use non-blocking assignments <= inside the always block for Q. Follow JK flip-flop truth table carefully.

4

Test the JK flip-flop by printing the output

Add a testbench module named testbench that instantiates jk_flip_flop. Initialize J, K, clk, and reset. Toggle clk every 5 time units. Apply a sequence of inputs to J and K to demonstrate the flip-flop behavior. Use $monitor to print J, K, clk, reset, and Q values.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        Q <= 0;
    end else begin
        if (J == 0 && K == 0) begin
            Q <= Q;
        end else if (J == 0 && K == 1) begin
            Q <= 0;
        end else if (J == 1 && K == 0) begin
            Q <= 1;
        end else if (J == 1 && K == 1) begin
            Q <= ~Q;
        end
    end
end

endmodule

// Your testbench code here

Need a hint?

Use a testbench with a clock toggling every 5 time units. Use $monitor to print signals. Apply different J and K values to see the flip-flop behavior.