JK flip-flop behavior in Verilog - Mini Project: Build & Apply

JK Flip-Flop Behavior

📖 Scenario: You are designing a simple digital circuit that uses a JK flip-flop to store and toggle a bit based on input signals.

🎯 Goal: Build a Verilog module that models the behavior of a JK flip-flop with asynchronous reset and clock input.

📋 What You'll Learn

Create a Verilog module named jk_flip_flop with inputs J, K, clk, and reset.

Add an output Q that holds the flip-flop state.

Implement the JK flip-flop behavior inside an always block triggered on the rising edge of clk or when reset is high.

On reset, Q should be set to 0.

On clock edge, update Q according to JK flip-flop rules: if J=K=0, hold state; if J=0 and K=1, reset Q; if J=1 and K=0, set Q; if J=K=1, toggle Q.

💡 Why This Matters

🌍 Real World

JK flip-flops are basic building blocks in digital electronics used for memory storage, counters, and state machines.

💼 Career

Understanding flip-flop behavior is essential for hardware design engineers and FPGA developers working on digital circuits.

1

Create the JK flip-flop module and declare inputs and output

Write a Verilog module named jk_flip_flop with inputs J, K, clk, and reset. Declare an output Q as a reg type.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

// Your code here

endmodule

Hint

Start by writing the module header with the exact input and output names and types.

2

Add an always block triggered on rising edge of clk or reset

Inside the jk_flip_flop module, add an always block triggered on the rising edge of clk or when reset is high.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

always @(posedge clk or posedge reset) begin
    // Your code here
end

endmodule

Hint

Use always @(posedge clk or posedge reset) to detect clock and reset events.

3

Implement reset and JK flip-flop behavior inside the always block

Inside the always block, write an if statement to set Q = 0 when reset is high. Otherwise, implement JK flip-flop logic: if J == 0 and K == 0, keep Q unchanged; if J == 0 and K == 1, set Q = 0; if J == 1 and K == 0, set Q = 1; if J == 1 and K == 1, toggle Q.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Your code here
    end else begin
        // Your code here
    end
end

endmodule

Hint

Use non-blocking assignments <= inside the always block for Q. Follow JK flip-flop truth table carefully.

4

Test the JK flip-flop by printing the output

Add a testbench module named testbench that instantiates jk_flip_flop. Initialize J, K, clk, and reset. Toggle clk every 5 time units. Apply a sequence of inputs to J and K to demonstrate the flip-flop behavior. Use $monitor to print J, K, clk, reset, and Q values.

Verilog

module jk_flip_flop(input J, input K, input clk, input reset, output reg Q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        Q <= 0;
    end else begin
        if (J == 0 && K == 0) begin
            Q <= Q;
        end else if (J == 0 && K == 1) begin
            Q <= 0;
        end else if (J == 1 && K == 0) begin
            Q <= 1;
        end else if (J == 1 && K == 1) begin
            Q <= ~Q;
        end
    end
end

endmodule

// Your testbench code here

Hint

Use a testbench with a clock toggling every 5 time units. Use $monitor to print signals. Apply different J and K values to see the flip-flop behavior.

Practice

1. What is the output behavior of a JK flip-flop when both inputs J and K are 0?

easy

A. The output toggles its state.

B. The output resets to 0.

C. The output sets to 1.

D. The output holds its previous state.

Solution

1. Step 1: Understand JK flip-flop input conditions

   When both J and K are 0, the flip-flop does not change its output.

2. Step 2: Recall JK flip-flop behavior for J=0 and K=0

   The output remains the same as the previous state, meaning it holds its value.

3. Final Answer:

   The output holds its previous state. -> Option D

4. Quick Check:

   J=0, K=0 means hold state [OK]

Hint: J=0 and K=0 means no change, output holds [OK]

Common Mistakes:

• Confusing hold with reset or set
• Thinking output toggles when inputs are zero
• Assuming output always resets on zero inputs

2. Which of the following is the correct Verilog sensitivity list for a JK flip-flop triggered on the rising edge of clock clk?

easy

A. always @(posedge clk or posedge reset)

B. always @(posedge clk)

C. always @(clk)

D. always @(negedge clk)

Solution

1. Step 1: Identify clock edge triggering

   JK flip-flops are usually triggered on the rising edge of the clock signal.

2. Step 2: Choose correct sensitivity list syntax

   In Verilog, rising edge is specified by posedge clk, so always @(posedge clk) is correct.

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge clk [OK]

Hint: posedge clk means rising edge trigger [OK]

Common Mistakes:

• Using negedge instead of posedge
• Missing edge keyword in sensitivity list
• Including unrelated signals without reason

3. Given the following Verilog code snippet for a JK flip-flop, what will be the output q after the clock rising edge if j=1, k=0, and previous q=0?

always @(posedge clk) begin
  case ({j,k})
    2'b00: q <= q;
    2'b01: q <= 0;
    2'b10: q <= 1;
    2'b11: q <= ~q;
  endcase
end

medium

A. 1

B. Toggle previous q

C. 0

D. No change

Solution

1. Step 1: Identify input combination and previous output

   Inputs are j=1, k=0, previous q=0.

2. Step 2: Match input to case statement

   For {j,k} = 2'b10, the code sets q to 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   J=1, K=0 sets q=1 [OK]

Hint: J=1 and K=0 sets output to 1 [OK]

Common Mistakes:

• Confusing toggle with set
• Ignoring previous q value
• Misreading case statement

4. Identify the error in this JK flip-flop Verilog code snippet:

always @(posedge clk) begin
  if (j == 1 && k == 1)
    q <= q;
  else if (j == 1)
    q <= 1;
  else if (k == 1)
    q <= 0;
end

medium

A. Missing sensitivity to reset signal.

B. Incorrect use of non-blocking assignment '<='.

C. The toggle condition is incorrect; it should invert q, not hold it.

D. The if-else structure is missing an else case for j=0 and k=0.

Solution

1. Step 1: Analyze toggle condition for j=1 and k=1

   The code holds q when both j and k are 1, but JK flip-flop should toggle q in this case.

2. Step 2: Verify other conditions and assignments

   Other conditions set or reset q correctly, but toggle logic is wrong.

3. Final Answer:

   The toggle condition is incorrect; it should invert q, not hold it. -> Option C

4. Quick Check:

   J=1 and K=1 toggles q, not holds [OK]

Hint: J=K=1 means toggle output, not hold [OK]

Common Mistakes:

• Assuming hold on J=K=1 instead of toggle
• Ignoring toggle logic in JK flip-flop
• Confusing blocking and non-blocking assignments

5. You want to design a JK flip-flop in Verilog that asynchronously resets q to 0 when reset is high, otherwise behaves normally on the rising edge of clk. Which code snippet correctly implements this behavior?

hard

A. always @(posedge clk or posedge reset) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

B. always @(posedge clk) begin\n if (reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

C. always @(posedge reset or posedge clk) begin\n if (reset) q <= 1;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

D. always @(posedge clk or negedge reset) begin\n if (!reset) q <= 0;\n else case ({j,k})\n 2'b00: q <= q;\n 2'b01: q <= 0;\n 2'b10: q <= 1;\n 2'b11: q <= ~q;\n endcase\nend

Solution

1. Step 1: Identify asynchronous reset sensitivity

   The reset is asynchronous, so it must be in the sensitivity list with posedge reset.

2. Step 2: Check reset behavior and JK logic

   When reset is high, q is set to 0 immediately. Otherwise, JK flip-flop behavior is implemented correctly with case statement.

3. Final Answer:

   Code with sensitivity list @(posedge clk or posedge reset) and reset logic first. -> Option A

4. Quick Check:

   Asynchronous reset uses posedge reset in sensitivity list [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Placing reset only inside clock edge sensitivity
• Setting q to 1 on reset instead of 0
• Using negedge reset incorrectly for active-high reset