If-else in always blocks in Verilog - Step-by-Step Execution

Concept Flow - If-else in always blocks

Start always block

↓

Evaluate if condition

Yes No↓

Execute if block

↓

Update outputs

↓

End always block

The always block starts, checks the if condition, executes the matching branch, updates outputs, then ends.

Execution Sample

Verilog

always @(posedge clk) begin
  if (reset) begin
    q <= 0;
  end else begin
    q <= d;
  end
end

On each clock edge, if reset is high, q is set to 0; otherwise, q takes the value of d.

Execution Table

Step	Condition (reset)	Branch Taken	Action	q value
1	1 (true)	if	q <= 0	0
2	0 (false)	else	q <= d (assume d=5)	5
3	0 (false)	else	q <= d (assume d=10)	10
4	1 (true)	if	q <= 0	0
5	0 (false)	else	q <= d (assume d=3)	3

💡 Simulation ends after 5 clock cycles traced.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
reset	X	1	0	0	1	0
d	X	X	5	10	X	3
q	X	0	5	10	0	3

Key Moments - 3 Insights

Why does q get set to 0 when reset is 1, even if d has a value?

Because the if condition (reset == 1) is true, the always block executes the if branch (q <= 0), ignoring d. See execution_table rows 1 and 4.

What happens if reset is 0? Does q keep its old value?

No, q gets updated to d's value in the else branch. See execution_table rows 2, 3, and 5 where reset is 0 and q changes to d.

Is the else block mandatory after if in always blocks?

No, but if else is missing and if condition is false, q would keep its old value (no assignment). Here, else ensures q updates when reset is 0.

Visual Quiz - 3 Questions

Look at the execution_table at Step 3, what is the value of q?

A 0

B 5

C 10

D 3

💡 Hint

Check the 'q value' column at Step 3 in the execution_table.

At which step does the if condition become true again after being false?

A Step 4

B Step 3

C Step 2

D Step 5

💡 Hint

Look at the 'Condition (reset)' column in the execution_table to find when reset changes from 0 to 1.

If the else block was removed, what would happen when reset is 0?

A q would be set to 0

B q would keep its previous value

C q would be set to d

D Simulation would error

💡 Hint

Without else, if condition false means no assignment; check key_moments explanation about else necessity.

Concept Snapshot

always @(event) begin
  if (condition) begin
    // if block
  end else begin
    // else block
  end
end

- If condition true, execute if block
- Else execute else block
- Used for sequential logic triggered by events

Full Transcript

This visual execution shows how an if-else statement works inside a Verilog always block. The always block triggers on a clock edge. It checks the reset signal. If reset is 1, q is set to 0. If reset is 0, q takes the value of d. The execution table traces five clock cycles showing reset, d, and q values. The variable tracker shows how these variables change step by step. Key moments clarify why q changes or stays the same depending on reset and the presence of else. The quiz tests understanding of q's value at specific steps, when reset changes, and the role of else. The snapshot summarizes the syntax and behavior of if-else in always blocks.

Practice

1. What is the main purpose of using if-else statements inside always blocks in Verilog?

easy

A. To declare variables

B. To create loops

C. To control hardware behavior based on conditions

D. To define module ports

Solution

1. Step 1: Understand the role of always blocks

   always blocks describe hardware that reacts to changes in signals.

2. Step 2: Understand if-else inside always

   if-else lets hardware choose different actions based on conditions.

3. Final Answer:

   To control hardware behavior based on conditions -> Option C

4. Quick Check:

   if-else controls hardware actions = B [OK]

Hint: If-else decides hardware action by condition [OK]

Common Mistakes:

• Thinking if-else declares variables
• Confusing if-else with loops
• Using if-else to define ports

2. Which of the following is the correct syntax for an if-else statement inside an always block in Verilog?

easy

A. always @ (posedge clk) if (a) begin b = 1; end else b = 0

B. always @ (posedge clk) if (a) b = 1; else b = 0;

C. always @ (posedge clk) if a { b = 1; } else { b = 0; }

D. always (posedge clk) if a then b = 1 else b = 0;

Solution

1. Step 1: Check the correct sensitivity list syntax

   It must be always @ (posedge clk), not missing @ or parentheses.

2. Step 2: Check if-else syntax

   Condition must be in parentheses, and statements can be single-line without begin-end.

3. Final Answer:

   always @ (posedge clk) if (a) b = 1; else b = 0; -> Option B

4. Quick Check:

   Correct always and if-else syntax = D [OK]

Hint: Use @ and parentheses for always and if conditions [OK]

Common Mistakes:

• Omitting @ in always sensitivity
• Missing parentheses around condition
• Using braces {} instead of begin-end

3. What will be the value of out after the following code runs if sel = 1 and in = 5?

always @(*) begin
  if (sel == 1)
    out = in + 1;
  else
    out = in - 1;
end

medium

A. 4

B. 5

C. Undefined

D. 6

Solution

1. Step 1: Check the condition with given inputs

   Since sel == 1 is true, the first branch executes.

2. Step 2: Calculate the assigned value

   out = in + 1 = 5 + 1 = 6.

3. Final Answer:

   6 -> Option D

4. Quick Check:

   sel=1 triggers out=in+1=6 [OK]

Hint: Follow if condition and calculate assigned value [OK]

Common Mistakes:

• Ignoring the if condition value
• Subtracting instead of adding
• Assuming out is unchanged

4. Identify the error in this Verilog code snippet:

always @ (posedge clk) begin
  if (reset == 1)
    count = 0;
  else if (enable == 1)
    count = count + 1;
end

medium

A. Using blocking assignment = instead of non-blocking <=

B. No default else to cover all cases

C. Missing begin-end after else if

D. Incorrect sensitivity list

Solution

1. Step 1: Check assignment type inside clocked always

   Inside clocked blocks, non-blocking assignments (<=) should be used for registers.

2. Step 2: Verify other parts

   Sensitivity list and if-else structure are correct; missing else is allowed but not best practice.

3. Final Answer:

   Using blocking assignment = instead of non-blocking <= -> Option A

4. Quick Check:

   Clocked always needs non-blocking <= [OK]

Hint: Use <= for assignments in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Forgetting begin-end for multiple statements
• Ignoring missing else cases

5. You want to design a 2-bit saturating counter using an always block with if-else. The counter increments on enable and resets to 0 on reset. It saturates at 3 (does not wrap). Which code snippet correctly implements this behavior?

hard

A. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable && count < 3) count <= count + 1;
else count <= count;
end

B. always @ (posedge clk) begin
if (reset) count = 0;
else if (enable) count = (count == 3) ? 3 : count + 1;
end

C. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
if (count > 3) count <= 3;
end

D. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= (count == 3) ? 0 : count + 1;
end

Solution

1. Step 1: Check reset and enable behavior

   Reset sets count to 0; enable increments count only if less than 3.

2. Step 2: Verify saturation logic

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end increments only if count < 3, else holds count, correctly saturating at 3.

3. Step 3: Check assignment type and completeness

   Uses non-blocking <= and covers all cases with else count <= count.

4. Final Answer:

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end -> Option A

5. Quick Check:

   Saturate at 3 by conditional increment and hold = A [OK]

Hint: Increment only if less than max, else hold value [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Resetting incorrectly or missing saturation check
• Wrapping counter instead of saturating