If-else in always blocks in Verilog - Step-by-Step Execution

Concept Flow - If-else in always blocks

Start always block

↓

Evaluate if condition

Yes No↓

Execute if block

↓

Update outputs

↓

End always block

The always block starts, checks the if condition, executes the matching branch, updates outputs, then ends.

Execution Sample

Verilog

always @(posedge clk) begin
  if (reset) begin
    q <= 0;
  end else begin
    q <= d;
  end
end

On each clock edge, if reset is high, q is set to 0; otherwise, q takes the value of d.

Execution Table

Step	Condition (reset)	Branch Taken	Action	q value
1	1 (true)	if	q <= 0	0
2	0 (false)	else	q <= d (assume d=5)	5
3	0 (false)	else	q <= d (assume d=10)	10
4	1 (true)	if	q <= 0	0
5	0 (false)	else	q <= d (assume d=3)	3

💡 Simulation ends after 5 clock cycles traced.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
reset	X	1	0	0	1	0
d	X	X	5	10	X	3
q	X	0	5	10	0	3

Key Moments - 3 Insights

Why does q get set to 0 when reset is 1, even if d has a value?

Because the if condition (reset == 1) is true, the always block executes the if branch (q <= 0), ignoring d. See execution_table rows 1 and 4.

What happens if reset is 0? Does q keep its old value?

No, q gets updated to d's value in the else branch. See execution_table rows 2, 3, and 5 where reset is 0 and q changes to d.

Is the else block mandatory after if in always blocks?

No, but if else is missing and if condition is false, q would keep its old value (no assignment). Here, else ensures q updates when reset is 0.

Visual Quiz - 3 Questions

Look at the execution_table at Step 3, what is the value of q?

A 0

B 5

C 10

D 3

💡 Hint

Check the 'q value' column at Step 3 in the execution_table.

At which step does the if condition become true again after being false?

A Step 4

B Step 3

C Step 2

D Step 5

💡 Hint

Look at the 'Condition (reset)' column in the execution_table to find when reset changes from 0 to 1.

If the else block was removed, what would happen when reset is 0?

A q would be set to 0

B q would keep its previous value

C q would be set to d

D Simulation would error

💡 Hint

Without else, if condition false means no assignment; check key_moments explanation about else necessity.

Concept Snapshot

always @(event) begin
  if (condition) begin
    // if block
  end else begin
    // else block
  end
end

- If condition true, execute if block
- Else execute else block
- Used for sequential logic triggered by events

Full Transcript

This visual execution shows how an if-else statement works inside a Verilog always block. The always block triggers on a clock edge. It checks the reset signal. If reset is 1, q is set to 0. If reset is 0, q takes the value of d. The execution table traces five clock cycles showing reset, d, and q values. The variable tracker shows how these variables change step by step. Key moments clarify why q changes or stays the same depending on reset and the presence of else. The quiz tests understanding of q's value at specific steps, when reset changes, and the role of else. The snapshot summarizes the syntax and behavior of if-else in always blocks.