If-else in always blocks in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to start an always block triggered on the positive edge of clk.

Verilog

always @([1]) begin
  // code here
end

Drag options to blanks, or click blank then click option'

Anegedge clk

Bposedge clk

Cclk

Dposedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' without edge keyword causes continuous sensitivity.

Using 'negedge clk' triggers on falling edge, not rising.

The always block should trigger on the positive edge of the clock signal, so posedge clk is correct.

2fill in blank

medium

Complete the if statement to check if reset is active high inside an always block.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    // reset logic
  end
end

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Areset == 0

Breset = 1

Creset != 1

Dreset == 1

Attempts:

3 left

💡 Hint

Common Mistakes

Using single '=' instead of '==' causes syntax errors.

Checking for reset == 0 is active low, not active high.

To check if reset is active high, use reset == 1. The single equals sign is an assignment, not a comparison.

3fill in blank

hard

Fix the error in the else statement syntax inside the always block.

Verilog

always @(posedge clk) begin
  if (reset == 1) begin
    q <= 0;
  end [1] begin
    q <= d;
  end
end

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Aelse

Belsif

Celse if

Delseif

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'elsif' or 'elseif' causes syntax errors.

Writing 'else if' without condition is incorrect here.

The correct keyword for the alternative condition is else. Verilog does not use elsif or elseif.

4fill in blank

hard

Fill both blanks to complete a nested if-else inside an always block checking enable and reset.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    if ([2]) begin
      q <= 0;
    end else begin
      q <= d;
    end
  end
end

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Aenable

Breset == 1

Creset == 0

Denable == 0

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing reset active low with active high.

Using 'enable == 0' instead of 'enable'.

The outer if checks if enable is true. The inner if checks if reset == 1 to reset q.

5fill in blank

hard

Fill all three blanks to complete a synchronous reset and load enable logic inside an always block.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    q <= 0;
  end else if ([2]) begin
    q <= [3];
  end
end

Drag options to blanks, or click blank then click option'

Areset == 1

Bload == 1

Cd

Denable == 1

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'enable' instead of 'load' for loading data.

Assigning 'enable == 1' to q instead of data signal.

The first condition checks if reset is active high. The second checks if load is active high. Then q loads the value d.

Practice

1. What is the main purpose of using if-else statements inside always blocks in Verilog?

easy

A. To declare variables

B. To create loops

C. To control hardware behavior based on conditions

D. To define module ports

Solution

1. Step 1: Understand the role of always blocks

   always blocks describe hardware that reacts to changes in signals.

2. Step 2: Understand if-else inside always

   if-else lets hardware choose different actions based on conditions.

3. Final Answer:

   To control hardware behavior based on conditions -> Option C

4. Quick Check:

   if-else controls hardware actions = B [OK]

Hint: If-else decides hardware action by condition [OK]

Common Mistakes:

• Thinking if-else declares variables
• Confusing if-else with loops
• Using if-else to define ports

2. Which of the following is the correct syntax for an if-else statement inside an always block in Verilog?

easy

A. always @ (posedge clk) if (a) begin b = 1; end else b = 0

B. always @ (posedge clk) if (a) b = 1; else b = 0;

C. always @ (posedge clk) if a { b = 1; } else { b = 0; }

D. always (posedge clk) if a then b = 1 else b = 0;

Solution

1. Step 1: Check the correct sensitivity list syntax

   It must be always @ (posedge clk), not missing @ or parentheses.

2. Step 2: Check if-else syntax

   Condition must be in parentheses, and statements can be single-line without begin-end.

3. Final Answer:

   always @ (posedge clk) if (a) b = 1; else b = 0; -> Option B

4. Quick Check:

   Correct always and if-else syntax = D [OK]

Hint: Use @ and parentheses for always and if conditions [OK]

Common Mistakes:

• Omitting @ in always sensitivity
• Missing parentheses around condition
• Using braces {} instead of begin-end

3. What will be the value of out after the following code runs if sel = 1 and in = 5?

always @(*) begin
  if (sel == 1)
    out = in + 1;
  else
    out = in - 1;
end

medium

A. 4

B. 5

C. Undefined

D. 6

Solution

1. Step 1: Check the condition with given inputs

   Since sel == 1 is true, the first branch executes.

2. Step 2: Calculate the assigned value

   out = in + 1 = 5 + 1 = 6.

3. Final Answer:

   6 -> Option D

4. Quick Check:

   sel=1 triggers out=in+1=6 [OK]

Hint: Follow if condition and calculate assigned value [OK]

Common Mistakes:

• Ignoring the if condition value
• Subtracting instead of adding
• Assuming out is unchanged

4. Identify the error in this Verilog code snippet:

always @ (posedge clk) begin
  if (reset == 1)
    count = 0;
  else if (enable == 1)
    count = count + 1;
end

medium

A. Using blocking assignment = instead of non-blocking <=

B. No default else to cover all cases

C. Missing begin-end after else if

D. Incorrect sensitivity list

Solution

1. Step 1: Check assignment type inside clocked always

   Inside clocked blocks, non-blocking assignments (<=) should be used for registers.

2. Step 2: Verify other parts

   Sensitivity list and if-else structure are correct; missing else is allowed but not best practice.

3. Final Answer:

   Using blocking assignment = instead of non-blocking <= -> Option A

4. Quick Check:

   Clocked always needs non-blocking <= [OK]

Hint: Use <= for assignments in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Forgetting begin-end for multiple statements
• Ignoring missing else cases

5. You want to design a 2-bit saturating counter using an always block with if-else. The counter increments on enable and resets to 0 on reset. It saturates at 3 (does not wrap). Which code snippet correctly implements this behavior?

hard

A. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable && count < 3) count <= count + 1;
else count <= count;
end

B. always @ (posedge clk) begin
if (reset) count = 0;
else if (enable) count = (count == 3) ? 3 : count + 1;
end

C. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
if (count > 3) count <= 3;
end

D. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= (count == 3) ? 0 : count + 1;
end

Solution

1. Step 1: Check reset and enable behavior

   Reset sets count to 0; enable increments count only if less than 3.

2. Step 2: Verify saturation logic

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end increments only if count < 3, else holds count, correctly saturating at 3.

3. Step 3: Check assignment type and completeness

   Uses non-blocking <= and covers all cases with else count <= count.

4. Final Answer:

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end -> Option A

5. Quick Check:

   Saturate at 3 by conditional increment and hold = A [OK]

Hint: Increment only if less than max, else hold value [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Resetting incorrectly or missing saturation check
• Wrapping counter instead of saturating