If-else in always blocks in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to start an always block triggered on the positive edge of clk.

Verilog

always @([1]) begin
  // code here
end

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Anegedge clk

Bposedge clk

Cclk

Dposedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' without edge keyword causes continuous sensitivity.

Using 'negedge clk' triggers on falling edge, not rising.

The always block should trigger on the positive edge of the clock signal, so posedge clk is correct.

2fill in blank

medium

Complete the if statement to check if reset is active high inside an always block.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    // reset logic
  end
end

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Areset == 0

Breset = 1

Creset != 1

Dreset == 1

Attempts:

3 left

💡 Hint

Common Mistakes

Using single '=' instead of '==' causes syntax errors.

Checking for reset == 0 is active low, not active high.

To check if reset is active high, use reset == 1. The single equals sign is an assignment, not a comparison.

3fill in blank

hard

Fix the error in the else statement syntax inside the always block.

Verilog

always @(posedge clk) begin
  if (reset == 1) begin
    q <= 0;
  end [1] begin
    q <= d;
  end
end

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Aelse

Belsif

Celse if

Delseif

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'elsif' or 'elseif' causes syntax errors.

Writing 'else if' without condition is incorrect here.

The correct keyword for the alternative condition is else. Verilog does not use elsif or elseif.

4fill in blank

hard

Fill both blanks to complete a nested if-else inside an always block checking enable and reset.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    if ([2]) begin
      q <= 0;
    end else begin
      q <= d;
    end
  end
end

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Aenable

Breset == 1

Creset == 0

Denable == 0

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing reset active low with active high.

Using 'enable == 0' instead of 'enable'.

The outer if checks if enable is true. The inner if checks if reset == 1 to reset q.

5fill in blank

hard

Fill all three blanks to complete a synchronous reset and load enable logic inside an always block.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    q <= 0;
  end else if ([2]) begin
    q <= [3];
  end
end

Drag options to blanks, or click blank then click option'

Areset == 1

Bload == 1

Cd

Denable == 1

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'enable' instead of 'load' for loading data.

Assigning 'enable == 1' to q instead of data signal.

The first condition checks if reset is active high. The second checks if load is active high. Then q loads the value d.