If-else in always blocks in Verilog - Mini Project: Build & Apply

If-else in always blocks

📖 Scenario: You are designing a simple digital circuit that controls an LED based on a switch input. The LED should turn on when the switch is pressed and turn off when it is not pressed.

🎯 Goal: Build a Verilog module that uses an always block with if-else statements to control an LED output based on a switch input.

📋 What You'll Learn

Create a module named led_control with inputs and outputs

Use an always block triggered by the switch input

Use if-else inside the always block to set the LED output

Print the LED output value at the end

💡 Why This Matters

🌍 Real World

Controlling LEDs or other devices based on input signals is common in digital electronics and embedded systems.

💼 Career

Understanding if-else in always blocks is essential for hardware design engineers working with FPGA or ASIC development.

1

Create the module and inputs/outputs

Write a Verilog module named led_control with an input switch and an output led. Declare led as a reg type.

Verilog

module led_control(input switch, output reg led);
// Your code here
endmodule

Need a hint?

Remember to declare led as reg because it will be assigned inside an always block.

2

Add the always block triggered by switch

Inside the led_control module, add an always block that is triggered on any change of switch.

Verilog

module led_control(input switch, output reg led);

// Add always block triggered by switch

endmodule

Need a hint?

Use always @(switch) to trigger the block whenever switch changes.

3

Use if-else to control the LED output

Inside the always block, write an if-else statement that sets led to 1 if switch is 1, otherwise sets led to 0.

Verilog

module led_control(input switch, output reg led);
    always @(switch) begin
        // Add if-else to set led
    end
endmodule

Need a hint?

Use if (switch == 1) to check the switch state and assign led accordingly.

4

Print the LED output value

Add a testbench module named testbench that instantiates led_control. In an initial block, assign switch to 0 and 1 with delays, and use $display to print the led value after each change.

Verilog

module led_control(input switch, output reg led);
    always @(switch) begin
        if (switch == 1) begin
            led = 1;
        end else begin
            led = 0;
        end
    end
endmodule

// Add testbench module below

Need a hint?

Use $display to print the values of switch and led after delays in the testbench.