If-else in always blocks in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of an always block in Verilog?

An always block is used to describe behavior that should happen whenever certain signals change. It helps model sequential or combinational logic by running the code inside whenever the specified signals in the sensitivity list change.

beginner

How does an if-else statement work inside an always block?

Inside an always block, an if-else statement checks a condition and executes one block of code if the condition is true, and another block if it is false. This helps decide which signals to assign based on conditions.

intermediate

Why should you use non-blocking assignments (<=) inside sequential always blocks?

Non-blocking assignments (<=) allow all assignments to happen in parallel at the end of the time step, which models real hardware registers correctly and avoids race conditions.

intermediate

What happens if you forget the else part in an if-else inside an always block?

If you omit the else, the signal might keep its old value unintentionally, causing inferred latches or unexpected behavior in hardware.

beginner

Example: What does this code do?

always @(posedge clk) begin
  if (reset) count <= 0;
  else count <= count + 1;
end

This code resets the count to 0 when reset is true at the rising edge of clk. Otherwise, it increments count by 1 on each clock cycle.

In Verilog, which keyword starts a block that runs whenever signals change?

A always

B if

C module

D assign

The always block runs its code whenever signals in its sensitivity list change.

Inside an always block, what does an if-else statement do?

A Starts a loop

B Declares a new module

C Checks a condition and chooses which code to run

D Assigns a value permanently

An if-else checks a condition and runs code based on whether it is true or false.

Which assignment operator models registers correctly inside a clocked always block?

A <code>=</code> (blocking)

B <code>&lt;=</code> (non-blocking)

C <code>==</code>

D <code>!=</code>

Non-blocking assignments (<=) model registers by updating all values simultaneously at the end of the time step.

What risk do you face if you omit the else in an if-else inside an always block?

A Inferred latches causing unintended memory

B Syntax error

C Faster simulation

D No effect

Omitting else can cause inferred latches, which means the hardware remembers old values unexpectedly.

What does this code do?

always @(posedge clk) begin
  if (reset) count <= 0;
  else count <= count + 1;
end

A Does nothing

B Counts down from reset

C Assigns count to reset value always

D Resets count on reset, else increments count each clock

The code resets count to 0 when reset is true, otherwise increments it on each clock rising edge.

Explain how an if-else statement inside an always block controls signal assignments in Verilog.

Think about how hardware decides what value to hold based on conditions.

Describe why non-blocking assignments are preferred inside clocked always blocks with if-else statements.

Consider how hardware registers update all at once on a clock edge.

Practice

1. What is the main purpose of using if-else statements inside always blocks in Verilog?

easy

A. To declare variables

B. To create loops

C. To control hardware behavior based on conditions

D. To define module ports

Solution

1. Step 1: Understand the role of always blocks

   always blocks describe hardware that reacts to changes in signals.

2. Step 2: Understand if-else inside always

   if-else lets hardware choose different actions based on conditions.

3. Final Answer:

   To control hardware behavior based on conditions -> Option C

4. Quick Check:

   if-else controls hardware actions = B [OK]

Hint: If-else decides hardware action by condition [OK]

Common Mistakes:

• Thinking if-else declares variables
• Confusing if-else with loops
• Using if-else to define ports

2. Which of the following is the correct syntax for an if-else statement inside an always block in Verilog?

easy

A. always @ (posedge clk) if (a) begin b = 1; end else b = 0

B. always @ (posedge clk) if (a) b = 1; else b = 0;

C. always @ (posedge clk) if a { b = 1; } else { b = 0; }

D. always (posedge clk) if a then b = 1 else b = 0;

Solution

1. Step 1: Check the correct sensitivity list syntax

   It must be always @ (posedge clk), not missing @ or parentheses.

2. Step 2: Check if-else syntax

   Condition must be in parentheses, and statements can be single-line without begin-end.

3. Final Answer:

   always @ (posedge clk) if (a) b = 1; else b = 0; -> Option B

4. Quick Check:

   Correct always and if-else syntax = D [OK]

Hint: Use @ and parentheses for always and if conditions [OK]

Common Mistakes:

• Omitting @ in always sensitivity
• Missing parentheses around condition
• Using braces {} instead of begin-end

3. What will be the value of out after the following code runs if sel = 1 and in = 5?

always @(*) begin
  if (sel == 1)
    out = in + 1;
  else
    out = in - 1;
end

medium

A. 4

B. 5

C. Undefined

D. 6

Solution

1. Step 1: Check the condition with given inputs

   Since sel == 1 is true, the first branch executes.

2. Step 2: Calculate the assigned value

   out = in + 1 = 5 + 1 = 6.

3. Final Answer:

   6 -> Option D

4. Quick Check:

   sel=1 triggers out=in+1=6 [OK]

Hint: Follow if condition and calculate assigned value [OK]

Common Mistakes:

• Ignoring the if condition value
• Subtracting instead of adding
• Assuming out is unchanged

4. Identify the error in this Verilog code snippet:

always @ (posedge clk) begin
  if (reset == 1)
    count = 0;
  else if (enable == 1)
    count = count + 1;
end

medium

A. Using blocking assignment = instead of non-blocking <=

B. No default else to cover all cases

C. Missing begin-end after else if

D. Incorrect sensitivity list

Solution

1. Step 1: Check assignment type inside clocked always

   Inside clocked blocks, non-blocking assignments (<=) should be used for registers.

2. Step 2: Verify other parts

   Sensitivity list and if-else structure are correct; missing else is allowed but not best practice.

3. Final Answer:

   Using blocking assignment = instead of non-blocking <= -> Option A

4. Quick Check:

   Clocked always needs non-blocking <= [OK]

Hint: Use <= for assignments in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Forgetting begin-end for multiple statements
• Ignoring missing else cases

5. You want to design a 2-bit saturating counter using an always block with if-else. The counter increments on enable and resets to 0 on reset. It saturates at 3 (does not wrap). Which code snippet correctly implements this behavior?

hard

A. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable && count < 3) count <= count + 1;
else count <= count;
end

B. always @ (posedge clk) begin
if (reset) count = 0;
else if (enable) count = (count == 3) ? 3 : count + 1;
end

C. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
if (count > 3) count <= 3;
end

D. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= (count == 3) ? 0 : count + 1;
end

Solution

1. Step 1: Check reset and enable behavior

   Reset sets count to 0; enable increments count only if less than 3.

2. Step 2: Verify saturation logic

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end increments only if count < 3, else holds count, correctly saturating at 3.

3. Step 3: Check assignment type and completeness

   Uses non-blocking <= and covers all cases with else count <= count.

4. Final Answer:

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end -> Option A

5. Quick Check:

   Saturate at 3 by conditional increment and hold = A [OK]

Hint: Increment only if less than max, else hold value [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Resetting incorrectly or missing saturation check
• Wrapping counter instead of saturating