If-else in always blocks in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of an always block in Verilog?

An always block is used to describe behavior that should happen whenever certain signals change. It helps model sequential or combinational logic by running the code inside whenever the specified signals in the sensitivity list change.

beginner

How does an if-else statement work inside an always block?

Inside an always block, an if-else statement checks a condition and executes one block of code if the condition is true, and another block if it is false. This helps decide which signals to assign based on conditions.

intermediate

Why should you use non-blocking assignments (<=) inside sequential always blocks?

Non-blocking assignments (<=) allow all assignments to happen in parallel at the end of the time step, which models real hardware registers correctly and avoids race conditions.

intermediate

What happens if you forget the else part in an if-else inside an always block?

If you omit the else, the signal might keep its old value unintentionally, causing inferred latches or unexpected behavior in hardware.

beginner

Example: What does this code do?<br>

always @(posedge clk) begin
  if (reset) count <= 0;
  else count <= count + 1;
end

This code resets the count to 0 when reset is true at the rising edge of clk. Otherwise, it increments count by 1 on each clock cycle.

In Verilog, which keyword starts a block that runs whenever signals change?

A always

B if

C module

D assign

The always block runs its code whenever signals in its sensitivity list change.

Inside an always block, what does an if-else statement do?

A Starts a loop

B Declares a new module

C Checks a condition and chooses which code to run

D Assigns a value permanently

An if-else checks a condition and runs code based on whether it is true or false.

Which assignment operator models registers correctly inside a clocked always block?

A <code>=</code> (blocking)

B <code>&lt;=</code> (non-blocking)

C <code>==</code>

D <code>!=</code>

Non-blocking assignments (<=) model registers by updating all values simultaneously at the end of the time step.

What risk do you face if you omit the else in an if-else inside an always block?

A Inferred latches causing unintended memory

B Syntax error

C Faster simulation

D No effect

Omitting else can cause inferred latches, which means the hardware remembers old values unexpectedly.

What does this code do?<br>

always @(posedge clk) begin
  if (reset) count <= 0;
  else count <= count + 1;
end

A Does nothing

B Counts down from reset

C Assigns count to reset value always

D Resets count on reset, else increments count each clock

The code resets count to 0 when reset is true, otherwise increments it on each clock rising edge.

Explain how an if-else statement inside an always block controls signal assignments in Verilog.

Think about how hardware decides what value to hold based on conditions.

Describe why non-blocking assignments are preferred inside clocked always blocks with if-else statements.

Consider how hardware registers update all at once on a clock edge.