If-else in always blocks in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of if-else in always block with clock edge

What is the value of q after the positive edge of clk when d = 1 and reset = 0?

Verilog

module test(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 0;
    else if (d)
      q <= 1;
    else
      q <= 0;
  end
endmodule

A q = 1

B q = 0

C q retains previous value

D q toggles its value

💡 Hint

Check the order of if-else conditions and the values of inputs at clock edge.

When reset is 0 and d is 1 at the positive clock edge, the always block sets q to 1 because the else if (d) condition is true.

❓ Predict Output

intermediate

Behavior of nested if-else in always block

Given the inputs enable = 1, mode = 0, and reset = 0, what is the value of out after the always block executes?

Verilog

module nested_if(input enable, input mode, input reset, output reg out);
  always @(*) begin
    if (reset)
      out = 0;
    else begin
      if (enable) begin
        if (mode)
          out = 1;
        else
          out = 0;
      end else
        out = 0;
    end
  end
endmodule

A out retains previous value

B out = 1

C out = 0

D out is undefined

💡 Hint

Trace the nested if-else conditions carefully with given inputs.

reset is 0, enable is 1, mode is 0, so the inner if (mode) is false, setting out to 0.

🔧 Debug

advanced

Identify the error in if-else usage inside always block

What error will this Verilog code produce when synthesized or simulated?

Verilog

module error_example(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset == 1)
      q <= 0;
    else
      q <= d;
  end
endmodule

A SyntaxError: Missing semicolon after if statement

B SyntaxError: Missing parentheses around if condition

C No error, code runs correctly

D RuntimeError: q is not assigned in all branches

💡 Hint

Check the syntax of the if statement condition.

In Verilog, the if condition must be enclosed in parentheses. Missing parentheses cause a syntax error.

❓ Predict Output

advanced

Output of if-else with blocking and non-blocking assignments

What is the value of q after the always block executes on a positive clock edge if d = 1 and reset = 0?

Verilog

module blocking_nonblocking(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q = 0;
    else
      q <= d;
  end
endmodule

A q = 0

B q retains previous value

C q is unknown (X)

D q = 1

💡 Hint

Understand difference between blocking (=) and non-blocking (<=) assignments.

On reset, q is assigned 0 immediately (blocking). On clock edge with reset=0, q is updated to d (1) using non-blocking assignment.

🧠 Conceptual

expert

Effect of missing else in if-else chain inside always block

Consider this always block snippet:

always @(posedge clk) begin
  if (reset)
    q <= 0;
  if (enable)
    q <= d;
end

What is the behavior of q when both reset and enable are high at the same clock edge?

A q is set to d because the second if overwrites the first assignment

B q is set to 0 because the first if executes and second is ignored

C q retains previous value because assignments conflict

D q is unknown (X) due to conflicting assignments

💡 Hint

Remember that both if statements execute independently if no else is used.

Both if statements execute independently. The second assignment to q (q <= d) overwrites the first (q <= 0) in the same clock cycle.

Practice

1. What is the main purpose of using if-else statements inside always blocks in Verilog?

easy

A. To declare variables

B. To create loops

C. To control hardware behavior based on conditions

D. To define module ports

Solution

1. Step 1: Understand the role of always blocks

   always blocks describe hardware that reacts to changes in signals.

2. Step 2: Understand if-else inside always

   if-else lets hardware choose different actions based on conditions.

3. Final Answer:

   To control hardware behavior based on conditions -> Option C

4. Quick Check:

   if-else controls hardware actions = B [OK]

Hint: If-else decides hardware action by condition [OK]

Common Mistakes:

• Thinking if-else declares variables
• Confusing if-else with loops
• Using if-else to define ports

2. Which of the following is the correct syntax for an if-else statement inside an always block in Verilog?

easy

A. always @ (posedge clk) if (a) begin b = 1; end else b = 0

B. always @ (posedge clk) if (a) b = 1; else b = 0;

C. always @ (posedge clk) if a { b = 1; } else { b = 0; }

D. always (posedge clk) if a then b = 1 else b = 0;

Solution

1. Step 1: Check the correct sensitivity list syntax

   It must be always @ (posedge clk), not missing @ or parentheses.

2. Step 2: Check if-else syntax

   Condition must be in parentheses, and statements can be single-line without begin-end.

3. Final Answer:

   always @ (posedge clk) if (a) b = 1; else b = 0; -> Option B

4. Quick Check:

   Correct always and if-else syntax = D [OK]

Hint: Use @ and parentheses for always and if conditions [OK]

Common Mistakes:

• Omitting @ in always sensitivity
• Missing parentheses around condition
• Using braces {} instead of begin-end

3. What will be the value of out after the following code runs if sel = 1 and in = 5?

always @(*) begin
  if (sel == 1)
    out = in + 1;
  else
    out = in - 1;
end

medium

A. 4

B. 5

C. Undefined

D. 6

Solution

1. Step 1: Check the condition with given inputs

   Since sel == 1 is true, the first branch executes.

2. Step 2: Calculate the assigned value

   out = in + 1 = 5 + 1 = 6.

3. Final Answer:

   6 -> Option D

4. Quick Check:

   sel=1 triggers out=in+1=6 [OK]

Hint: Follow if condition and calculate assigned value [OK]

Common Mistakes:

• Ignoring the if condition value
• Subtracting instead of adding
• Assuming out is unchanged

4. Identify the error in this Verilog code snippet:

always @ (posedge clk) begin
  if (reset == 1)
    count = 0;
  else if (enable == 1)
    count = count + 1;
end

medium

A. Using blocking assignment = instead of non-blocking <=

B. No default else to cover all cases

C. Missing begin-end after else if

D. Incorrect sensitivity list

Solution

1. Step 1: Check assignment type inside clocked always

   Inside clocked blocks, non-blocking assignments (<=) should be used for registers.

2. Step 2: Verify other parts

   Sensitivity list and if-else structure are correct; missing else is allowed but not best practice.

3. Final Answer:

   Using blocking assignment = instead of non-blocking <= -> Option A

4. Quick Check:

   Clocked always needs non-blocking <= [OK]

Hint: Use <= for assignments in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Forgetting begin-end for multiple statements
• Ignoring missing else cases

5. You want to design a 2-bit saturating counter using an always block with if-else. The counter increments on enable and resets to 0 on reset. It saturates at 3 (does not wrap). Which code snippet correctly implements this behavior?

hard

A. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable && count < 3) count <= count + 1;
else count <= count;
end

B. always @ (posedge clk) begin
if (reset) count = 0;
else if (enable) count = (count == 3) ? 3 : count + 1;
end

C. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
if (count > 3) count <= 3;
end

D. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= (count == 3) ? 0 : count + 1;
end

Solution

1. Step 1: Check reset and enable behavior

   Reset sets count to 0; enable increments count only if less than 3.

2. Step 2: Verify saturation logic

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end increments only if count < 3, else holds count, correctly saturating at 3.

3. Step 3: Check assignment type and completeness

   Uses non-blocking <= and covers all cases with else count <= count.

4. Final Answer:

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end -> Option A

5. Quick Check:

   Saturate at 3 by conditional increment and hold = A [OK]

Hint: Increment only if less than max, else hold value [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Resetting incorrectly or missing saturation check
• Wrapping counter instead of saturating