If-else in always blocks in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of if-else in always block with clock edge

What is the value of q after the positive edge of clk when d = 1 and reset = 0?

Verilog

module test(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 0;
    else if (d)
      q <= 1;
    else
      q <= 0;
  end
endmodule

A q = 1

B q = 0

C q retains previous value

D q toggles its value

💡 Hint

Check the order of if-else conditions and the values of inputs at clock edge.

When reset is 0 and d is 1 at the positive clock edge, the always block sets q to 1 because the else if (d) condition is true.

❓ Predict Output

intermediate

Behavior of nested if-else in always block

Given the inputs enable = 1, mode = 0, and reset = 0, what is the value of out after the always block executes?

Verilog

module nested_if(input enable, input mode, input reset, output reg out);
  always @(*) begin
    if (reset)
      out = 0;
    else begin
      if (enable) begin
        if (mode)
          out = 1;
        else
          out = 0;
      end else
        out = 0;
    end
  end
endmodule

A out retains previous value

B out = 1

C out = 0

D out is undefined

💡 Hint

Trace the nested if-else conditions carefully with given inputs.

reset is 0, enable is 1, mode is 0, so the inner if (mode) is false, setting out to 0.

🔧 Debug

advanced

Identify the error in if-else usage inside always block

What error will this Verilog code produce when synthesized or simulated?

Verilog

module error_example(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset == 1)
      q <= 0;
    else
      q <= d;
  end
endmodule

A SyntaxError: Missing semicolon after if statement

B SyntaxError: Missing parentheses around if condition

C No error, code runs correctly

D RuntimeError: q is not assigned in all branches

💡 Hint

Check the syntax of the if statement condition.

In Verilog, the if condition must be enclosed in parentheses. Missing parentheses cause a syntax error.

❓ Predict Output

advanced

Output of if-else with blocking and non-blocking assignments

What is the value of q after the always block executes on a positive clock edge if d = 1 and reset = 0?

Verilog

module blocking_nonblocking(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q = 0;
    else
      q <= d;
  end
endmodule

A q = 0

B q retains previous value

C q is unknown (X)

D q = 1

💡 Hint

Understand difference between blocking (=) and non-blocking (<=) assignments.

On reset, q is assigned 0 immediately (blocking). On clock edge with reset=0, q is updated to d (1) using non-blocking assignment.

🧠 Conceptual

expert

Effect of missing else in if-else chain inside always block

Consider this always block snippet:

always @(posedge clk) begin
  if (reset)
    q <= 0;
  if (enable)
    q <= d;
end

What is the behavior of q when both reset and enable are high at the same clock edge?

A q is set to d because the second if overwrites the first assignment

B q is set to 0 because the first if executes and second is ignored

C q retains previous value because assignments conflict

D q is unknown (X) due to conflicting assignments

💡 Hint

Remember that both if statements execute independently if no else is used.

Both if statements execute independently. The second assignment to q (q <= d) overwrites the first (q <= 0) in the same clock cycle.