D flip-flop with synchronous reset in Verilog - Step-by-Step Execution

Concept Flow - D flip-flop with synchronous reset

Clock Rising Edge

↓

Check Reset

↓

Set Q=0

↓

Output Q

On each rising clock edge, the flip-flop checks the reset signal. If reset is high, output Q is set to 0; otherwise, Q takes the value of input D.

Execution Sample

Verilog

always @(posedge clk) begin
  if (reset) q <= 0;
  else q <= d;
end

This code updates output q on the clock's rising edge, resetting q to 0 if reset is high, else copying input d.

Execution Table

Step	clk	reset	d	Condition (reset?)	Action	q (new value)
1	rising edge	0	1	No	q <= d	1
2	rising edge	1	0	Yes	q <= 0	0
3	rising edge	0	1	No	q <= d	1
4	rising edge	0	0	No	q <= d	0
5	rising edge	1	1	Yes	q <= 0	0
6	no edge	0	1	N/A	No change	0

💡 No further clock rising edges, so no more updates to q.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
q	X (unknown)	1	0	1	0	0	0
reset	0	0	1	0	0	1	0
d	X	1	0	1	0	1	1

Key Moments - 3 Insights

Why does q change only on clock rising edges and not when reset or d changes?

Because the flip-flop updates q only at the rising edge of clk, as shown in the execution_table steps where only 'rising edge' clk triggers q changes.

What happens if reset is high and d is 1 at the same clock edge?

The reset condition has priority, so q is set to 0 regardless of d, as seen in step 2 and 5 of the execution_table.

Why does q remain the same when there is no clock edge even if d or reset changes?

Because the flip-flop is edge-triggered, it ignores input changes without a clock rising edge, as shown in step 6 where q stays 0.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of q after step 3?

A 0

B 1

C X (unknown)

D Cannot determine

💡 Hint

Check the 'q (new value)' column in row for step 3.

At which step does the reset signal cause q to be set to 0?

A Step 2

B Step 4

C Step 1

D Step 6

💡 Hint

Look for steps where 'Condition (reset?)' is Yes and 'q (new value)' is 0.

If reset was always 0, what would q be after step 5?

A 0

B X (unknown)

C 1

D No change

💡 Hint

Refer to variable_tracker for q values when reset is 0 and d is 1.

Concept Snapshot

D flip-flop with synchronous reset:
- On clock rising edge, check reset.
- If reset=1, set q=0.
- Else, set q=d.
- q changes only on clock edges.
- Reset has priority over d input.

Full Transcript

This visual trace shows a D flip-flop with synchronous reset in Verilog. On each rising clock edge, the flip-flop checks if reset is high. If yes, it sets output q to 0. Otherwise, q takes the value of input d. The execution table walks through six steps showing clk edges, reset and d values, conditions checked, actions taken, and q's new value. The variable tracker shows how q, reset, and d change over time. Key moments clarify why q updates only on clock edges, reset priority, and no change without clock edge. The quiz tests understanding of q values at specific steps and reset effects. The snapshot summarizes the behavior and rules of this flip-flop type.