D flip-flop with synchronous reset in Verilog - Step-by-Step Execution

Concept Flow - D flip-flop with synchronous reset

Clock Rising Edge

↓

Check Reset

↓

Set Q=0

↓

Output Q

On each rising clock edge, the flip-flop checks the reset signal. If reset is high, output Q is set to 0; otherwise, Q takes the value of input D.

Execution Sample

Verilog

always @(posedge clk) begin
  if (reset) q <= 0;
  else q <= d;
end

This code updates output q on the clock's rising edge, resetting q to 0 if reset is high, else copying input d.

Execution Table

Step	clk	reset	d	Condition (reset?)	Action	q (new value)
1	rising edge	0	1	No	q <= d	1
2	rising edge	1	0	Yes	q <= 0	0
3	rising edge	0	1	No	q <= d	1
4	rising edge	0	0	No	q <= d	0
5	rising edge	1	1	Yes	q <= 0	0
6	no edge	0	1	N/A	No change	0

💡 No further clock rising edges, so no more updates to q.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
q	X (unknown)	1	0	1	0	0	0
reset	0	0	1	0	0	1	0
d	X	1	0	1	0	1	1

Key Moments - 3 Insights

Why does q change only on clock rising edges and not when reset or d changes?

Because the flip-flop updates q only at the rising edge of clk, as shown in the execution_table steps where only 'rising edge' clk triggers q changes.

What happens if reset is high and d is 1 at the same clock edge?

The reset condition has priority, so q is set to 0 regardless of d, as seen in step 2 and 5 of the execution_table.

Why does q remain the same when there is no clock edge even if d or reset changes?

Because the flip-flop is edge-triggered, it ignores input changes without a clock rising edge, as shown in step 6 where q stays 0.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of q after step 3?

A 0

B 1

C X (unknown)

D Cannot determine

💡 Hint

Check the 'q (new value)' column in row for step 3.

At which step does the reset signal cause q to be set to 0?

A Step 2

B Step 4

C Step 1

D Step 6

💡 Hint

Look for steps where 'Condition (reset?)' is Yes and 'q (new value)' is 0.

If reset was always 0, what would q be after step 5?

A 0

B X (unknown)

C 1

D No change

💡 Hint

Refer to variable_tracker for q values when reset is 0 and d is 1.

Concept Snapshot

D flip-flop with synchronous reset:
- On clock rising edge, check reset.
- If reset=1, set q=0.
- Else, set q=d.
- q changes only on clock edges.
- Reset has priority over d input.

Full Transcript

This visual trace shows a D flip-flop with synchronous reset in Verilog. On each rising clock edge, the flip-flop checks if reset is high. If yes, it sets output q to 0. Otherwise, q takes the value of input d. The execution table walks through six steps showing clk edges, reset and d values, conditions checked, actions taken, and q's new value. The variable tracker shows how q, reset, and d change over time. Key moments clarify why q updates only on clock edges, reset priority, and no change without clock edge. The quiz tests understanding of q values at specific steps and reset effects. The snapshot summarizes the behavior and rules of this flip-flop type.

Practice

1. What does a D flip-flop with synchronous reset do when the reset signal is active?

easy

A. It clears the stored data immediately when reset is active.

B. It stores the inverse of the input data.

C. It ignores the reset signal and keeps the data.

D. It clears the stored data only on the clock edge.

Solution

1. Step 1: Understand synchronous reset behavior

   A synchronous reset affects the flip-flop only at the clock edge, not immediately.

2. Step 2: Compare reset types

   Asynchronous reset clears data immediately, but synchronous reset waits for clock edge.

3. Final Answer:

   It clears the stored data only on the clock edge. -> Option D

4. Quick Check:

   Synchronous reset = clear on clock edge [OK]

Hint: Synchronous reset acts only at clock edges [OK]

Common Mistakes:

• Confusing synchronous with asynchronous reset
• Thinking reset clears data immediately
• Assuming reset stores input data

2. Which of the following is the correct Verilog syntax for a D flip-flop with synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

B. always @(negedge clk) begin if (!reset) q <= d; else q <= 0; end

C. always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

D. always @(reset) begin if (reset) q <= 0; else q <= d; end

Solution

1. Step 1: Identify synchronous reset sensitivity list

   Synchronous reset triggers only on clock edge, so only posedge clk is in sensitivity list.

2. Step 2: Check reset condition inside always block

   Reset is checked inside the block, not in sensitivity list, matching synchronous reset behavior.

3. Final Answer:

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end -> Option C

4. Quick Check:

   Synchronous reset inside posedge clk block [OK]

Hint: Synchronous reset inside posedge clk always block [OK]

Common Mistakes:

• Including reset in sensitivity list (asynchronous reset)
• Using reset in sensitivity list but coding synchronous reset
• Using negedge clk incorrectly

3. Given the following Verilog code, what is the value of q after the second rising edge of clk if reset is 1 at the first clock and 0 at the second?

reg q;
always @(posedge clk) begin
  if (reset) q <= 0;
  else q <= d;
end

medium

A. 1

B. d (input value)

C. 0

D. Undefined

Solution

1. Step 1: Analyze first clock edge with reset=1

   At first posedge clk, reset=1, so q is set to 0.

2. Step 2: Analyze second clock edge with reset=0

   At second posedge clk, reset=0, so q takes value of d input.

3. Final Answer:

   d (input value) -> Option B

4. Quick Check:

   Reset active clears q, then q follows d [OK]

Hint: Reset clears q only at clock edge, then q follows d [OK]

Common Mistakes:

• Assuming reset clears q immediately
• Thinking q stays 0 after reset deactivates
• Confusing asynchronous reset behavior

4. Identify the error in this Verilog code for a D flip-flop with synchronous reset:

always @(posedge clk or posedge reset) begin
  if (reset) q <= 0;
  else q <= d;
end

medium

A. Reset should not be in the sensitivity list for synchronous reset.

B. The assignment operator should be '=' instead of '<='.

C. The clock edge should be negedge, not posedge.

D. The reset condition should be checked after the else statement.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset triggers only on clock edge, so reset must NOT be in sensitivity list.

2. Step 2: Confirm correct sensitivity list

   Only posedge clk should be in sensitivity list for synchronous reset.

3. Final Answer:

   Reset should not be in the sensitivity list for synchronous reset. -> Option A

4. Quick Check:

   Synchronous reset excludes reset from sensitivity list [OK]

Hint: Synchronous reset excludes reset from sensitivity list [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Using blocking assignment instead of non-blocking
• Checking reset condition incorrectly

5. You want to design a D flip-flop with synchronous reset that sets output q to 0 on reset and otherwise stores input d. Which Verilog code correctly implements this with minimal logic and proper timing?

hard

A. always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

B. always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

C. always @(posedge clk) begin if (reset) q <= d; else q <= 0; end

D. always @(posedge reset) begin if (reset) q <= 0; else q <= d; end

Solution

1. Step 1: Confirm synchronous reset sensitivity list

   For synchronous reset, only posedge clk is in sensitivity list.

2. Step 2: Check reset logic inside always block

   Reset condition sets q to 0 when active; else q follows d input.

3. Step 3: Verify minimal and correct logic

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end matches synchronous reset behavior with minimal logic and correct timing.

4. Final Answer:

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end -> Option A

5. Quick Check:

   Synchronous reset inside posedge clk block with correct logic [OK]

Hint: Use posedge clk only and check reset inside block [OK]

Common Mistakes:

• Including reset in sensitivity list (asynchronous reset)
• Using negedge clk incorrectly
• Inverting reset logic