D flip-flop with synchronous reset in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the D flip-flop module with synchronous reset.

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge [1]) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

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Aclk

Bd

Creset

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset' instead of 'clk' in the sensitivity list.

Using 'd' or 'q' in the sensitivity list which is incorrect.

The flip-flop triggers on the positive edge of the clock signal 'clk'.

2fill in blank

medium

Complete the code to assign the output 'q' when reset is active.

Verilog

always @(posedge clk) begin
  if (reset) q <= [1];
  else q <= d;
end

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A1

B0

Cd

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Setting 'q' to 1 instead of 0 on reset.

Assigning 'q' to 'd' or 'q' inside the reset condition.

When reset is active, the output 'q' is set to 0 synchronously.

3fill in blank

hard

Fix the error in the sensitivity list to make the reset synchronous.

Verilog

always @([1]) begin
  if (reset) q <= 0;
  else q <= d;
end

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Anegedge reset

Bposedge reset or posedge clk

Cposedge clk

Dreset or clk

Attempts:

3 left

💡 Hint

Common Mistakes

Including reset in the sensitivity list, which makes reset asynchronous.

Using 'negedge reset' which is asynchronous.

For synchronous reset, the always block triggers only on the clock's positive edge.

4fill in blank

hard

Fill both blanks to complete the module declaration and output definition.

Verilog

module dff_sync_reset([1], output reg [2]);
  input clk, reset, d;
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

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Ainput clk, reset, d

Binput q

Cq

Dd

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring 'q' as input instead of output.

Forgetting to declare inputs properly.

The module inputs are declared as 'input clk, reset, d' and output 'q' is declared as 'output reg q'.

5fill in blank

hard

Fill all three blanks to complete the always block with synchronous reset and data assignment.

Verilog

always @([1]) begin
  if ([2]) q <= 0;
  else q <= [3];
end

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Aposedge clk

Breset

Cd

Dposedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge reset' in sensitivity list which makes reset asynchronous.

Assigning 'q' to 'reset' or 'clk' instead of 'd'.

The always block triggers on 'posedge clk', checks 'reset' condition, and assigns 'd' to 'q' otherwise.