D flip-flop with synchronous reset in Verilog - Mini Project: Build & Apply

D flip-flop with synchronous reset

📖 Scenario: In digital electronics, a D flip-flop stores a single bit of data. It changes its output only on the clock's rising edge. A synchronous reset means the flip-flop resets its output to 0 only when the clock ticks and the reset signal is active.

🎯 Goal: You will build a simple D flip-flop module in Verilog with a synchronous reset input. This flip-flop will store the input d on the rising edge of the clock clk, and reset the output q to 0 when reset is high during a clock edge.

📋 What You'll Learn

Create a module named d_flip_flop with inputs d, clk, reset and output q

Use an always block triggered on the rising edge of clk

Inside the always block, check if reset is high to set q to 0

Otherwise, assign d to q

Use non-blocking assignments <= inside the always block

💡 Why This Matters

🌍 Real World

D flip-flops are fundamental building blocks in digital circuits used for memory, registers, and state machines.

💼 Career

Understanding flip-flops and synchronous resets is essential for hardware design engineers working with FPGAs and ASICs.

1

Create the module and declare inputs and output

Write a Verilog module named d_flip_flop with inputs d, clk, reset and output q. Declare q as a reg type.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

// Your code here

endmodule

Need a hint?

Start by writing the module header with the exact input and output names and types.

2

Add the always block triggered on rising edge of clk

Inside the d_flip_flop module, add an always block triggered on the rising edge of clk using always @(posedge clk).

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk) begin
    // Your code here
end

endmodule

Need a hint?

Use always @(posedge clk) to run code on the clock's rising edge.

3

Add synchronous reset logic inside the always block

Inside the always block, write an if statement that checks if reset is high. If yes, assign 0 to q using non-blocking assignment <=. Otherwise, assign d to q using non-blocking assignment.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk) begin
    // Your code here
end

endmodule

Need a hint?

Use if (reset) to check reset, and non-blocking assignments <= to update q.

4

Test the module by printing a simple simulation output

Add a testbench module named testbench that declares d, clk, reset as reg and q as wire. Instantiate d_flip_flop inside it. Initialize clk to 0 and toggle it every 5 time units. Apply a sequence of values to d and reset to show q changes. Use $monitor to print clk, reset, d, and q. Run the simulation for 30 time units.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk) begin
    if (reset) begin
        q <= 0;
    end else begin
        q <= d;
    end
end

endmodule

// Your testbench code here

Need a hint?

Use a testbench with clock toggling and $monitor to see how q changes with d and reset.