D flip-flop with synchronous reset in Verilog - Mini Project: Build & Apply

D flip-flop with synchronous reset

📖 Scenario: In digital electronics, a D flip-flop stores a single bit of data. It changes its output only on the clock's rising edge. A synchronous reset means the flip-flop resets its output to 0 only when the clock ticks and the reset signal is active.

🎯 Goal: You will build a simple D flip-flop module in Verilog with a synchronous reset input. This flip-flop will store the input d on the rising edge of the clock clk, and reset the output q to 0 when reset is high during a clock edge.

📋 What You'll Learn

Create a module named d_flip_flop with inputs d, clk, reset and output q

Use an always block triggered on the rising edge of clk

Inside the always block, check if reset is high to set q to 0

Otherwise, assign d to q

Use non-blocking assignments <= inside the always block

💡 Why This Matters

🌍 Real World

D flip-flops are fundamental building blocks in digital circuits used for memory, registers, and state machines.

💼 Career

Understanding flip-flops and synchronous resets is essential for hardware design engineers working with FPGAs and ASICs.

1

Create the module and declare inputs and output

Write a Verilog module named d_flip_flop with inputs d, clk, reset and output q. Declare q as a reg type.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

// Your code here

endmodule

Hint

Start by writing the module header with the exact input and output names and types.

2

Add the always block triggered on rising edge of clk

Inside the d_flip_flop module, add an always block triggered on the rising edge of clk using always @(posedge clk).

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk) begin
    // Your code here
end

endmodule

Hint

Use always @(posedge clk) to run code on the clock's rising edge.

3

Add synchronous reset logic inside the always block

Inside the always block, write an if statement that checks if reset is high. If yes, assign 0 to q using non-blocking assignment <=. Otherwise, assign d to q using non-blocking assignment.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk) begin
    // Your code here
end

endmodule

Hint

Use if (reset) to check reset, and non-blocking assignments <= to update q.

4

Test the module by printing a simple simulation output

Add a testbench module named testbench that declares d, clk, reset as reg and q as wire. Instantiate d_flip_flop inside it. Initialize clk to 0 and toggle it every 5 time units. Apply a sequence of values to d and reset to show q changes. Use $monitor to print clk, reset, d, and q. Run the simulation for 30 time units.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk) begin
    if (reset) begin
        q <= 0;
    end else begin
        q <= d;
    end
end

endmodule

// Your testbench code here

Hint

Use a testbench with clock toggling and $monitor to see how q changes with d and reset.

Practice

1. What does a D flip-flop with synchronous reset do when the reset signal is active?

easy

A. It clears the stored data immediately when reset is active.

B. It stores the inverse of the input data.

C. It ignores the reset signal and keeps the data.

D. It clears the stored data only on the clock edge.

Solution

1. Step 1: Understand synchronous reset behavior

   A synchronous reset affects the flip-flop only at the clock edge, not immediately.

2. Step 2: Compare reset types

   Asynchronous reset clears data immediately, but synchronous reset waits for clock edge.

3. Final Answer:

   It clears the stored data only on the clock edge. -> Option D

4. Quick Check:

   Synchronous reset = clear on clock edge [OK]

Hint: Synchronous reset acts only at clock edges [OK]

Common Mistakes:

• Confusing synchronous with asynchronous reset
• Thinking reset clears data immediately
• Assuming reset stores input data

2. Which of the following is the correct Verilog syntax for a D flip-flop with synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

B. always @(negedge clk) begin if (!reset) q <= d; else q <= 0; end

C. always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

D. always @(reset) begin if (reset) q <= 0; else q <= d; end

Solution

1. Step 1: Identify synchronous reset sensitivity list

   Synchronous reset triggers only on clock edge, so only posedge clk is in sensitivity list.

2. Step 2: Check reset condition inside always block

   Reset is checked inside the block, not in sensitivity list, matching synchronous reset behavior.

3. Final Answer:

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end -> Option C

4. Quick Check:

   Synchronous reset inside posedge clk block [OK]

Hint: Synchronous reset inside posedge clk always block [OK]

Common Mistakes:

• Including reset in sensitivity list (asynchronous reset)
• Using reset in sensitivity list but coding synchronous reset
• Using negedge clk incorrectly

3. Given the following Verilog code, what is the value of q after the second rising edge of clk if reset is 1 at the first clock and 0 at the second?

reg q;
always @(posedge clk) begin
  if (reset) q <= 0;
  else q <= d;
end

medium

A. 1

B. d (input value)

C. 0

D. Undefined

Solution

1. Step 1: Analyze first clock edge with reset=1

   At first posedge clk, reset=1, so q is set to 0.

2. Step 2: Analyze second clock edge with reset=0

   At second posedge clk, reset=0, so q takes value of d input.

3. Final Answer:

   d (input value) -> Option B

4. Quick Check:

   Reset active clears q, then q follows d [OK]

Hint: Reset clears q only at clock edge, then q follows d [OK]

Common Mistakes:

• Assuming reset clears q immediately
• Thinking q stays 0 after reset deactivates
• Confusing asynchronous reset behavior

4. Identify the error in this Verilog code for a D flip-flop with synchronous reset:

always @(posedge clk or posedge reset) begin
  if (reset) q <= 0;
  else q <= d;
end

medium

A. Reset should not be in the sensitivity list for synchronous reset.

B. The assignment operator should be '=' instead of '<='.

C. The clock edge should be negedge, not posedge.

D. The reset condition should be checked after the else statement.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset triggers only on clock edge, so reset must NOT be in sensitivity list.

2. Step 2: Confirm correct sensitivity list

   Only posedge clk should be in sensitivity list for synchronous reset.

3. Final Answer:

   Reset should not be in the sensitivity list for synchronous reset. -> Option A

4. Quick Check:

   Synchronous reset excludes reset from sensitivity list [OK]

Hint: Synchronous reset excludes reset from sensitivity list [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Using blocking assignment instead of non-blocking
• Checking reset condition incorrectly

5. You want to design a D flip-flop with synchronous reset that sets output q to 0 on reset and otherwise stores input d. Which Verilog code correctly implements this with minimal logic and proper timing?

hard

A. always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

B. always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

C. always @(posedge clk) begin if (reset) q <= d; else q <= 0; end

D. always @(posedge reset) begin if (reset) q <= 0; else q <= d; end

Solution

1. Step 1: Confirm synchronous reset sensitivity list

   For synchronous reset, only posedge clk is in sensitivity list.

2. Step 2: Check reset logic inside always block

   Reset condition sets q to 0 when active; else q follows d input.

3. Step 3: Verify minimal and correct logic

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end matches synchronous reset behavior with minimal logic and correct timing.

4. Final Answer:

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end -> Option A

5. Quick Check:

   Synchronous reset inside posedge clk block with correct logic [OK]

Hint: Use posedge clk only and check reset inside block [OK]

Common Mistakes:

• Including reset in sensitivity list (asynchronous reset)
• Using negedge clk incorrectly
• Inverting reset logic