D flip-flop with synchronous reset in Verilog - Time & Space Complexity

Time Complexity: D flip-flop with synchronous reset

O(n)

Understanding Time Complexity

We want to understand how the time it takes to run a D flip-flop with synchronous reset changes as input size changes.

Specifically, we ask: how does the number of operations grow when the circuit runs?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

module dff_sync_reset (
  input wire clk,
  input wire reset,
  input wire d,
  output reg q
);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

This code models a D flip-flop that updates its output on the clock's rising edge and resets synchronously when reset is high.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The flip-flop updates output on every clock rising edge.
• How many times: Once per clock cycle, repeating indefinitely as the clock runs.

How Execution Grows With Input

Explain the growth pattern intuitively.

Input Size (clock cycles)	Approx. Operations
10	10 updates
100	100 updates
1000	1000 updates

Pattern observation: The number of operations grows directly with the number of clock cycles, increasing steadily.

Final Time Complexity

Time Complexity: O(n)

This means the work done grows linearly with the number of clock cycles the flip-flop runs.

Common Mistake

[X] Wrong: "The flip-flop does many operations inside each clock cycle, so time grows faster than linearly."

[OK] Correct: Each clock cycle triggers only one update operation, so the work grows one-to-one with cycles, not more.

Interview Connect

Understanding how hardware elements like flip-flops behave over time helps you reason about circuit speed and design efficiency, a useful skill in many tech roles.

Self-Check

"What if the flip-flop had an asynchronous reset instead? How would the time complexity change?"