D flip-flop with synchronous reset in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of D flip-flop with synchronous reset

What is the output Q after the rising edge of the clock if D=1 and synchronous reset R=0?

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

// Initial state q=0, inputs: clk rising edge, reset=0, d=1

A Q = 0

B Q = 1

C Q retains previous value

D Q toggles

💡 Hint

Remember synchronous reset only affects Q on clock edge when reset=1.

Since reset=0, the flip-flop captures D=1 on the rising clock edge, so Q becomes 1.

❓ Predict Output

intermediate

Effect of synchronous reset on output

Given the D flip-flop with synchronous reset, what is the output Q after the clock rising edge if reset=1 and D=1?

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

// Initial state q=1, inputs: clk rising edge, reset=1, d=1

A Q = 1

B Q toggles

C Q retains previous value

D Q = 0

💡 Hint

Synchronous reset overrides D input on clock edge.

When reset=1 at clock edge, Q is set to 0 regardless of D.

🔧 Debug

advanced

Identify the error in D flip-flop with synchronous reset

Which option contains a syntax error in the Verilog code for a D flip-flop with synchronous reset?

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

A always @(posedge clk) begin if reset q <= 0; else q <= d; end

B always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

C always @(posedge clk) begin if (reset) q = 0; else q <= d; end

D dne ;d =< q esle ;0 =< q )teser( fi nigeb )klc egdesop(@ syawla

💡 Hint

Check the syntax of the if statement condition.

Option A misses parentheses around the if condition, causing a syntax error.

🧠 Conceptual

advanced

Behavior of synchronous reset in D flip-flop

What happens to the output Q of a D flip-flop with synchronous reset if reset is asserted asynchronously (not synchronized with clock)?

A Q resets only on the next clock rising edge when reset is asserted

B Q resets immediately when reset is asserted

C Q ignores reset signal completely

D Q toggles on reset assertion

💡 Hint

Synchronous reset affects output only at clock edges.

Synchronous reset changes Q only at the clock edge, so asynchronous assertion waits until clock edge.

🚀 Application

expert

Count number of times Q resets in a clock sequence

Given a D flip-flop with synchronous reset, clock cycles and reset signals as below, how many times does Q reset to 0? Clock edges: 5 rising edges Reset signals at edges: [0, 1, 0, 1, 0] D inputs at edges: [1, 1, 0, 0, 1] Initial Q=1

A 3 times

B 0 times

C 2 times

D 1 time

💡 Hint

Count how many clock edges have reset=1.

Q resets only on clock edges where reset=1, which happens twice (2nd and 4th edges).