D flip-flop with synchronous reset in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of D flip-flop with synchronous reset

What is the output Q after the rising edge of the clock if D=1 and synchronous reset R=0?

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

// Initial state q=0, inputs: clk rising edge, reset=0, d=1

A Q = 0

B Q = 1

C Q retains previous value

D Q toggles

💡 Hint

Remember synchronous reset only affects Q on clock edge when reset=1.

Since reset=0, the flip-flop captures D=1 on the rising clock edge, so Q becomes 1.

❓ Predict Output

intermediate

Effect of synchronous reset on output

Given the D flip-flop with synchronous reset, what is the output Q after the clock rising edge if reset=1 and D=1?

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

// Initial state q=1, inputs: clk rising edge, reset=1, d=1

A Q = 1

B Q toggles

C Q retains previous value

D Q = 0

💡 Hint

Synchronous reset overrides D input on clock edge.

When reset=1 at clock edge, Q is set to 0 regardless of D.

🔧 Debug

advanced

Identify the error in D flip-flop with synchronous reset

Which option contains a syntax error in the Verilog code for a D flip-flop with synchronous reset?

Verilog

module dff_sync_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

A always @(posedge clk) begin if reset q <= 0; else q <= d; end

B always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

C always @(posedge clk) begin if (reset) q = 0; else q <= d; end

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💡 Hint

Check the syntax of the if statement condition.

Option A misses parentheses around the if condition, causing a syntax error.

🧠 Conceptual

advanced

Behavior of synchronous reset in D flip-flop

What happens to the output Q of a D flip-flop with synchronous reset if reset is asserted asynchronously (not synchronized with clock)?

A Q resets only on the next clock rising edge when reset is asserted

B Q resets immediately when reset is asserted

C Q ignores reset signal completely

D Q toggles on reset assertion

💡 Hint

Synchronous reset affects output only at clock edges.

Synchronous reset changes Q only at the clock edge, so asynchronous assertion waits until clock edge.

🚀 Application

expert

Count number of times Q resets in a clock sequence

Given a D flip-flop with synchronous reset, clock cycles and reset signals as below, how many times does Q reset to 0? Clock edges: 5 rising edges Reset signals at edges: [0, 1, 0, 1, 0] D inputs at edges: [1, 1, 0, 0, 1] Initial Q=1

A 3 times

B 0 times

C 2 times

D 1 time

💡 Hint

Count how many clock edges have reset=1.

Q resets only on clock edges where reset=1, which happens twice (2nd and 4th edges).

Practice

1. What does a D flip-flop with synchronous reset do when the reset signal is active?

easy

A. It clears the stored data immediately when reset is active.

B. It stores the inverse of the input data.

C. It ignores the reset signal and keeps the data.

D. It clears the stored data only on the clock edge.

Solution

1. Step 1: Understand synchronous reset behavior

   A synchronous reset affects the flip-flop only at the clock edge, not immediately.

2. Step 2: Compare reset types

   Asynchronous reset clears data immediately, but synchronous reset waits for clock edge.

3. Final Answer:

   It clears the stored data only on the clock edge. -> Option D

4. Quick Check:

   Synchronous reset = clear on clock edge [OK]

Hint: Synchronous reset acts only at clock edges [OK]

Common Mistakes:

• Confusing synchronous with asynchronous reset
• Thinking reset clears data immediately
• Assuming reset stores input data

2. Which of the following is the correct Verilog syntax for a D flip-flop with synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

B. always @(negedge clk) begin if (!reset) q <= d; else q <= 0; end

C. always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

D. always @(reset) begin if (reset) q <= 0; else q <= d; end

Solution

1. Step 1: Identify synchronous reset sensitivity list

   Synchronous reset triggers only on clock edge, so only posedge clk is in sensitivity list.

2. Step 2: Check reset condition inside always block

   Reset is checked inside the block, not in sensitivity list, matching synchronous reset behavior.

3. Final Answer:

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end -> Option C

4. Quick Check:

   Synchronous reset inside posedge clk block [OK]

Hint: Synchronous reset inside posedge clk always block [OK]

Common Mistakes:

• Including reset in sensitivity list (asynchronous reset)
• Using reset in sensitivity list but coding synchronous reset
• Using negedge clk incorrectly

3. Given the following Verilog code, what is the value of q after the second rising edge of clk if reset is 1 at the first clock and 0 at the second?

reg q;
always @(posedge clk) begin
  if (reset) q <= 0;
  else q <= d;
end

medium

A. 1

B. d (input value)

C. 0

D. Undefined

Solution

1. Step 1: Analyze first clock edge with reset=1

   At first posedge clk, reset=1, so q is set to 0.

2. Step 2: Analyze second clock edge with reset=0

   At second posedge clk, reset=0, so q takes value of d input.

3. Final Answer:

   d (input value) -> Option B

4. Quick Check:

   Reset active clears q, then q follows d [OK]

Hint: Reset clears q only at clock edge, then q follows d [OK]

Common Mistakes:

• Assuming reset clears q immediately
• Thinking q stays 0 after reset deactivates
• Confusing asynchronous reset behavior

4. Identify the error in this Verilog code for a D flip-flop with synchronous reset:

always @(posedge clk or posedge reset) begin
  if (reset) q <= 0;
  else q <= d;
end

medium

A. Reset should not be in the sensitivity list for synchronous reset.

B. The assignment operator should be '=' instead of '<='.

C. The clock edge should be negedge, not posedge.

D. The reset condition should be checked after the else statement.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset triggers only on clock edge, so reset must NOT be in sensitivity list.

2. Step 2: Confirm correct sensitivity list

   Only posedge clk should be in sensitivity list for synchronous reset.

3. Final Answer:

   Reset should not be in the sensitivity list for synchronous reset. -> Option A

4. Quick Check:

   Synchronous reset excludes reset from sensitivity list [OK]

Hint: Synchronous reset excludes reset from sensitivity list [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Using blocking assignment instead of non-blocking
• Checking reset condition incorrectly

5. You want to design a D flip-flop with synchronous reset that sets output q to 0 on reset and otherwise stores input d. Which Verilog code correctly implements this with minimal logic and proper timing?

hard

A. always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

B. always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

C. always @(posedge clk) begin if (reset) q <= d; else q <= 0; end

D. always @(posedge reset) begin if (reset) q <= 0; else q <= d; end

Solution

1. Step 1: Confirm synchronous reset sensitivity list

   For synchronous reset, only posedge clk is in sensitivity list.

2. Step 2: Check reset logic inside always block

   Reset condition sets q to 0 when active; else q follows d input.

3. Step 3: Verify minimal and correct logic

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end matches synchronous reset behavior with minimal logic and correct timing.

4. Final Answer:

   always @(posedge clk) begin if (reset) q <= 0; else q <= d; end -> Option A

5. Quick Check:

   Synchronous reset inside posedge clk block with correct logic [OK]

Hint: Use posedge clk only and check reset inside block [OK]

Common Mistakes:

• Including reset in sensitivity list (asynchronous reset)
• Using negedge clk incorrectly
• Inverting reset logic