D flip-flop with clock edge in Verilog - Step-by-Step Execution

Concept Flow - D flip-flop with clock edge

Wait for clock edge

↓

Detect rising edge?

No→Wait

Yes↓

Capture D input

↓

Update Q output

↓

Hold Q until next clock edge

The D flip-flop waits for a rising clock edge, then captures the input D and updates output Q, holding it steady until the next clock edge.

Execution Sample

Verilog

module d_flip_flop(
  input clk,
  input d,
  output reg q
);
  always @(posedge clk) q <= d;
endmodule

This code defines a D flip-flop that updates output q to input d on the rising edge of clock clk.

Execution Table

Step	clk	d	posedge clk?	Action	q (output)
1	0	0	No	No update	x (unknown initial)
2	1	0	Yes	Capture d=0	0
3	1	1	No	No update	0
4	0	1	No	No update	0
5	1	1	Yes	Capture d=1	1
6	0	0	No	No update	1
7	1	0	Yes	Capture d=0	0

💡 Simulation ends after step 7; flip-flop updates only on rising clock edges.

Variable Tracker

Variable	Start	After Step 2	After Step 5	After Step 7
clk	0	1	1	1
d	0	0	1	0
q	x	0	1	0

Key Moments - 3 Insights

Why does q not change when clk is 1 but no rising edge occurs?

Because the flip-flop updates q only on the rising edge of clk, not when clk stays high (see steps 2 to 3 in execution_table).

What happens to q before the first clock edge?

q is unknown (x) initially and only gets a defined value after the first rising edge (step 2).

Why does q hold its value between clock edges?

Because the flip-flop only updates q on clock rising edges, it holds the last captured value otherwise (see steps 3,4,6).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of q after step 5?

A 0

B 1

C x

D Undefined

💡 Hint

Check the 'q (output)' column at step 5 in the execution_table.

At which step does the first rising edge of clk occur?

A Step 2

B Step 1

C Step 3

D Step 4

💡 Hint

Look at the 'posedge clk?' column in the execution_table.

If d was 1 at step 7, what would q be after step 7?

A 0

B x

C 1

D No change

💡 Hint

Refer to the action 'Capture d=...' on rising edges in the execution_table.

Concept Snapshot

D flip-flop captures input D on rising clock edge.
Syntax: always @(posedge clk) q <= d;
Q holds last captured value until next rising edge.
Initial q is unknown until first clock edge.
Used to store 1-bit data synchronized to clock.

Full Transcript

A D flip-flop waits for a rising clock edge to capture the input value D and update its output Q. Initially, Q is unknown. When the clock rises from 0 to 1, the flip-flop copies D to Q. Between clock edges, Q holds its value steady. This behavior is shown step-by-step in the execution table, where only at steps with a rising clock edge does Q change. This is important for storing data synchronized to a clock signal in digital circuits.

Practice

1.

What does a D flip-flop do in a digital circuit?

easy

A. Stores the input value on the rising edge of the clock

B. Generates a clock signal

C. Performs arithmetic operations

D. Resets the circuit asynchronously

Solution

1. Step 1: Understand the role of a D flip-flop

   A D flip-flop captures and stores the input value (D) at a specific clock event.

2. Step 2: Identify the clock event

   It stores the value on the rising edge (positive edge) of the clock signal.

3. Final Answer:

   Stores the input value on the rising edge of the clock -> Option A

4. Quick Check:

   D flip-flop stores input on clock rising edge [OK]

Hint: Remember: D flip-flop stores data at clock's rising edge [OK]

Common Mistakes:

• Confusing D flip-flop with clock generator
• Thinking it performs calculations
• Assuming it resets asynchronously

2.

Which of the following is the correct Verilog syntax to trigger a D flip-flop on the rising edge of the clock clk?

easy

A. always @(negedge clk)

B. always @(posedge clk)

C. always @(clk)

D. always @(clk posedge)

Solution

1. Step 1: Recall the correct event control syntax

   Verilog uses posedge to detect the rising edge of a signal.

2. Step 2: Match syntax with clock signal

   The correct syntax to trigger on rising edge of clk is always @(posedge clk).

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge [OK]

Hint: Use 'posedge' for rising edge in always block [OK]

Common Mistakes:

• Using negedge instead of posedge
• Omitting posedge keyword
• Incorrect event control syntax

3.

What will be the output q after the following Verilog code runs for one clock cycle if d = 1 and initial q = 0?

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

medium

A. q remains 0

B. q toggles between 0 and 1

C. q becomes undefined

D. q becomes 1

Solution

1. Step 1: Understand the behavior on posedge clk

   On the rising edge of clk, the flip-flop assigns d to q.

2. Step 2: Apply given inputs

   Since d = 1 and initial q = 0, after the clock edge, q updates to 1.

3. Final Answer:

   q becomes 1 -> Option D

4. Quick Check:

   D input 1 stored at clock edge = q 1 [OK]

Hint: On clock rising edge, q copies d value [OK]

Common Mistakes:

• Assuming q changes immediately without clock edge
• Thinking q toggles automatically
• Ignoring initial value of q

4.

Identify the error in this D flip-flop Verilog code snippet:

module dff(input clk, input d, output reg q);
  always @(clk) begin
    q <= d;
  end
endmodule

medium

A. Missing sensitivity to clock edge, should use posedge

B. Output q should not be reg

C. Input d should be reg type

D. No error, code is correct

Solution

1. Step 1: Check sensitivity list

   The code uses always @(clk), which triggers on any change of clk, not just edges.

2. Step 2: Correct edge sensitivity

   For a D flip-flop, it must trigger only on the rising edge: always @(posedge clk).

3. Final Answer:

   Missing sensitivity to clock edge, should use posedge -> Option A

4. Quick Check:

   Flip-flop triggers on posedge clk only [OK]

Hint: Use posedge in always block for flip-flop [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing reg and wire for outputs
• Assuming inputs must be reg

5.

You want to design a D flip-flop that resets q to 0 asynchronously when rst is high. Which Verilog code snippet correctly implements this behavior?

module dff(input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

hard

A. The sensitivity list is missing negedge rst

B. Reset should be checked only on clock edge, not asynchronously

C. This code correctly implements asynchronous reset

D. q should be assigned with blocking assignment (=) inside always

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clock or rising edge of reset, enabling asynchronous reset.

2. Step 2: Check reset logic

   If reset is high, q is set to 0 immediately, else q follows d on clock edge.

3. Final Answer:

   This code correctly implements asynchronous reset -> Option C

4. Quick Check:

   Asynchronous reset uses posedge rst in sensitivity list [OK]

Hint: Add posedge rst in sensitivity list for async reset [OK]

Common Mistakes:

• Checking reset only on clock edge (synchronous reset)
• Using blocking assignment for sequential logic
• Missing reset in sensitivity list