D flip-flop with clock edge in Verilog - Step-by-Step Execution

Concept Flow - D flip-flop with clock edge

Wait for clock edge

↓

Detect rising edge?

No→Wait

Yes↓

Capture D input

↓

Update Q output

↓

Hold Q until next clock edge

The D flip-flop waits for a rising clock edge, then captures the input D and updates output Q, holding it steady until the next clock edge.

Execution Sample

Verilog

module d_flip_flop(
  input clk,
  input d,
  output reg q
);
  always @(posedge clk) q <= d;
endmodule

This code defines a D flip-flop that updates output q to input d on the rising edge of clock clk.

Execution Table

Step	clk	d	posedge clk?	Action	q (output)
1	0	0	No	No update	x (unknown initial)
2	1	0	Yes	Capture d=0	0
3	1	1	No	No update	0
4	0	1	No	No update	0
5	1	1	Yes	Capture d=1	1
6	0	0	No	No update	1
7	1	0	Yes	Capture d=0	0

💡 Simulation ends after step 7; flip-flop updates only on rising clock edges.

Variable Tracker

Variable	Start	After Step 2	After Step 5	After Step 7
clk	0	1	1	1
d	0	0	1	0
q	x	0	1	0

Key Moments - 3 Insights

Why does q not change when clk is 1 but no rising edge occurs?

Because the flip-flop updates q only on the rising edge of clk, not when clk stays high (see steps 2 to 3 in execution_table).

What happens to q before the first clock edge?

q is unknown (x) initially and only gets a defined value after the first rising edge (step 2).

Why does q hold its value between clock edges?

Because the flip-flop only updates q on clock rising edges, it holds the last captured value otherwise (see steps 3,4,6).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of q after step 5?

A 0

B 1

C x

D Undefined

💡 Hint

Check the 'q (output)' column at step 5 in the execution_table.

At which step does the first rising edge of clk occur?

A Step 2

B Step 1

C Step 3

D Step 4

💡 Hint

Look at the 'posedge clk?' column in the execution_table.

If d was 1 at step 7, what would q be after step 7?

A 0

B x

C 1

D No change

💡 Hint

Refer to the action 'Capture d=...' on rising edges in the execution_table.

Concept Snapshot

D flip-flop captures input D on rising clock edge.
Syntax: always @(posedge clk) q <= d;
Q holds last captured value until next rising edge.
Initial q is unknown until first clock edge.
Used to store 1-bit data synchronized to clock.

Full Transcript

A D flip-flop waits for a rising clock edge to capture the input value D and update its output Q. Initially, Q is unknown. When the clock rises from 0 to 1, the flip-flop copies D to Q. Between clock edges, Q holds its value steady. This behavior is shown step-by-step in the execution table, where only at steps with a rising clock edge does Q change. This is important for storing data synchronized to a clock signal in digital circuits.