D flip-flop with clock edge in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a D flip-flop in digital circuits?

A D flip-flop is a memory device that captures the value of the input (D) at a specific clock edge and holds it until the next clock edge.

beginner

Which clock edge does a positive-edge triggered D flip-flop respond to?

It responds to the rising edge of the clock signal, which is when the clock changes from 0 to 1.

intermediate

Explain the role of the clock signal in a D flip-flop.

The clock signal controls when the D flip-flop captures the input value. The flip-flop updates its output only at the specified clock edge, ensuring synchronized data storage.

beginner

What happens to the output Q of a D flip-flop if the clock does not have an edge?

The output Q remains unchanged and holds the last captured value until the next clock edge occurs.

intermediate

Write a simple Verilog code snippet for a positive-edge triggered D flip-flop.

module d_flip_flop(input wire clk, input wire d, output reg q); always @(posedge clk) begin q <= d; end endmodule

What does the 'posedge' keyword in Verilog indicate?

A No clock edge

B Negative (falling) edge of the clock

C Any change in the clock

D Positive (rising) edge of the clock

The 'posedge' keyword triggers the block on the rising edge of the clock signal.

In a D flip-flop, when is the input 'D' value transferred to output 'Q'?

A When reset is active

B Continuously

C At the clock edge

D When enable is low

The D flip-flop captures the input only at the clock edge, not continuously.

What will happen if you use 'negedge clk' instead of 'posedge clk' in a D flip-flop?

A Flip-flop triggers on falling edge of clock

B Flip-flop triggers on rising edge of clock

C Flip-flop triggers on both edges

D Flip-flop does not trigger

'negedge' means the flip-flop triggers on the falling (negative) edge of the clock.

Which statement best describes the output behavior of a D flip-flop between clock edges?

A Output holds the last value

B Output changes randomly

C Output follows input continuously

D Output resets to zero

Between clock edges, the output remains stable and holds the last captured value.

What is the purpose of using a D flip-flop in digital circuits?

A To amplify signals

B To store and synchronize data

C To generate clock signals

D To perform arithmetic operations

D flip-flops are used to store data and synchronize it with the clock signal.

Describe how a D flip-flop works with a clock edge to store data.

Think about when the flip-flop reads input and when it keeps the output stable.

Write a simple Verilog code example of a positive-edge triggered D flip-flop and explain each part.

Focus on how the always block uses the clock edge to update output.