D flip-flop with clock edge in Verilog - Mini Project: Build & Apply

D Flip-Flop with Clock Edge in Verilog

📖 Scenario: You are designing a simple digital circuit that stores a single bit of data. This circuit is called a D flip-flop. It changes its output only when the clock signal changes from low to high (rising edge).

🎯 Goal: Build a D flip-flop module in Verilog that updates its output q on the rising edge of the clock clk based on the input d.

📋 What You'll Learn

Create a module named d_flip_flop with inputs d and clk and output q

Use an always block triggered on the rising edge of clk

Inside the always block, assign d to q

Test the module with a simple testbench that changes d and clk signals

Print the output q to verify correct behavior

💡 Why This Matters

🌍 Real World

D flip-flops are basic building blocks in digital electronics used to store bits in memory, registers, and counters.

💼 Career

Understanding flip-flops is essential for hardware design engineers and anyone working with digital circuit design and FPGA programming.

1

Create the D Flip-Flop Module

Write a Verilog module named d_flip_flop with inputs d and clk and an output q. Declare q as a reg type.

Verilog

module d_flip_flop(input d, input clk, output reg q);
// Your code here
endmodule

Need a hint?

Start by declaring the module and its ports exactly as described.

2

Add the Clock Edge Trigger

Inside the d_flip_flop module, add an always block that triggers on the rising edge of clk using always @(posedge clk).

Verilog

module d_flip_flop(input d, input clk, output reg q);
    // Add always block triggered on rising edge of clk
    // Your code here
endmodule

Need a hint?

Use always @(posedge clk) to detect the rising edge of the clock.

3

Assign Input to Output on Clock Edge

Inside the always @(posedge clk) block, assign the input d to the output q using a non-blocking assignment q <= d;.

Verilog

module d_flip_flop(input d, input clk, output reg q);
    always @(posedge clk) begin
        // Assign d to q here
        // Your code here
    end
endmodule

Need a hint?

Use q <= d; inside the always block to update the output on the clock edge.

4

Test the D Flip-Flop Module

Write a testbench module named testbench that declares reg d, reg clk, and wire q. Instantiate d_flip_flop with these signals. Create an initial block that sets clk to 0 and toggles it every 5 time units. Change d at different times. Use $monitor to print clk, d, and q.

Verilog

module d_flip_flop(input d, input clk, output reg q);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

// Your testbench code here

Need a hint?

Use initial blocks to create clock and input signals. Use $monitor to print signal changes.