D flip-flop with clock edge in Verilog - Mini Project: Build & Apply

D Flip-Flop with Clock Edge in Verilog

📖 Scenario: You are designing a simple digital circuit that stores a single bit of data. This circuit is called a D flip-flop. It changes its output only when the clock signal changes from low to high (rising edge).

🎯 Goal: Build a D flip-flop module in Verilog that updates its output q on the rising edge of the clock clk based on the input d.

📋 What You'll Learn

Create a module named d_flip_flop with inputs d and clk and output q

Use an always block triggered on the rising edge of clk

Inside the always block, assign d to q

Test the module with a simple testbench that changes d and clk signals

Print the output q to verify correct behavior

💡 Why This Matters

🌍 Real World

D flip-flops are basic building blocks in digital electronics used to store bits in memory, registers, and counters.

💼 Career

Understanding flip-flops is essential for hardware design engineers and anyone working with digital circuit design and FPGA programming.

1

Create the D Flip-Flop Module

Write a Verilog module named d_flip_flop with inputs d and clk and an output q. Declare q as a reg type.

Verilog

module d_flip_flop(input d, input clk, output reg q);
// Your code here
endmodule

Hint

Start by declaring the module and its ports exactly as described.

2

Add the Clock Edge Trigger

Inside the d_flip_flop module, add an always block that triggers on the rising edge of clk using always @(posedge clk).

Verilog

module d_flip_flop(input d, input clk, output reg q);
    // Add always block triggered on rising edge of clk
    // Your code here
endmodule

Hint

Use always @(posedge clk) to detect the rising edge of the clock.

3

Assign Input to Output on Clock Edge

Inside the always @(posedge clk) block, assign the input d to the output q using a non-blocking assignment q <= d;.

Verilog

module d_flip_flop(input d, input clk, output reg q);
    always @(posedge clk) begin
        // Assign d to q here
        // Your code here
    end
endmodule

Hint

Use q <= d; inside the always block to update the output on the clock edge.

4

Test the D Flip-Flop Module

Write a testbench module named testbench that declares reg d, reg clk, and wire q. Instantiate d_flip_flop with these signals. Create an initial block that sets clk to 0 and toggles it every 5 time units. Change d at different times. Use $monitor to print clk, d, and q.

Verilog

module d_flip_flop(input d, input clk, output reg q);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

// Your testbench code here

Hint

Use initial blocks to create clock and input signals. Use $monitor to print signal changes.

Practice

1.

What does a D flip-flop do in a digital circuit?

easy

A. Stores the input value on the rising edge of the clock

B. Generates a clock signal

C. Performs arithmetic operations

D. Resets the circuit asynchronously

Solution

1. Step 1: Understand the role of a D flip-flop

   A D flip-flop captures and stores the input value (D) at a specific clock event.

2. Step 2: Identify the clock event

   It stores the value on the rising edge (positive edge) of the clock signal.

3. Final Answer:

   Stores the input value on the rising edge of the clock -> Option A

4. Quick Check:

   D flip-flop stores input on clock rising edge [OK]

Hint: Remember: D flip-flop stores data at clock's rising edge [OK]

Common Mistakes:

• Confusing D flip-flop with clock generator
• Thinking it performs calculations
• Assuming it resets asynchronously

2.

Which of the following is the correct Verilog syntax to trigger a D flip-flop on the rising edge of the clock clk?

easy

A. always @(negedge clk)

B. always @(posedge clk)

C. always @(clk)

D. always @(clk posedge)

Solution

1. Step 1: Recall the correct event control syntax

   Verilog uses posedge to detect the rising edge of a signal.

2. Step 2: Match syntax with clock signal

   The correct syntax to trigger on rising edge of clk is always @(posedge clk).

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge [OK]

Hint: Use 'posedge' for rising edge in always block [OK]

Common Mistakes:

• Using negedge instead of posedge
• Omitting posedge keyword
• Incorrect event control syntax

3.

What will be the output q after the following Verilog code runs for one clock cycle if d = 1 and initial q = 0?

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

medium

A. q remains 0

B. q toggles between 0 and 1

C. q becomes undefined

D. q becomes 1

Solution

1. Step 1: Understand the behavior on posedge clk

   On the rising edge of clk, the flip-flop assigns d to q.

2. Step 2: Apply given inputs

   Since d = 1 and initial q = 0, after the clock edge, q updates to 1.

3. Final Answer:

   q becomes 1 -> Option D

4. Quick Check:

   D input 1 stored at clock edge = q 1 [OK]

Hint: On clock rising edge, q copies d value [OK]

Common Mistakes:

• Assuming q changes immediately without clock edge
• Thinking q toggles automatically
• Ignoring initial value of q

4.

Identify the error in this D flip-flop Verilog code snippet:

module dff(input clk, input d, output reg q);
  always @(clk) begin
    q <= d;
  end
endmodule

medium

A. Missing sensitivity to clock edge, should use posedge

B. Output q should not be reg

C. Input d should be reg type

D. No error, code is correct

Solution

1. Step 1: Check sensitivity list

   The code uses always @(clk), which triggers on any change of clk, not just edges.

2. Step 2: Correct edge sensitivity

   For a D flip-flop, it must trigger only on the rising edge: always @(posedge clk).

3. Final Answer:

   Missing sensitivity to clock edge, should use posedge -> Option A

4. Quick Check:

   Flip-flop triggers on posedge clk only [OK]

Hint: Use posedge in always block for flip-flop [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing reg and wire for outputs
• Assuming inputs must be reg

5.

You want to design a D flip-flop that resets q to 0 asynchronously when rst is high. Which Verilog code snippet correctly implements this behavior?

module dff(input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

hard

A. The sensitivity list is missing negedge rst

B. Reset should be checked only on clock edge, not asynchronously

C. This code correctly implements asynchronous reset

D. q should be assigned with blocking assignment (=) inside always

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clock or rising edge of reset, enabling asynchronous reset.

2. Step 2: Check reset logic

   If reset is high, q is set to 0 immediately, else q follows d on clock edge.

3. Final Answer:

   This code correctly implements asynchronous reset -> Option C

4. Quick Check:

   Asynchronous reset uses posedge rst in sensitivity list [OK]

Hint: Add posedge rst in sensitivity list for async reset [OK]

Common Mistakes:

• Checking reset only on clock edge (synchronous reset)
• Using blocking assignment for sequential logic
• Missing reset in sensitivity list