D flip-flop with clock edge in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the D flip-flop module with inputs and output.

Verilog

module d_flip_flop([1], output reg q);
  // input d, clk;
endmodule

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Ainput wire d, clk

Boutput d, clk

Cinput reg d, clk

Dinput d, clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using output instead of input for inputs.

Declaring inputs as reg which is incorrect.

In Verilog, inputs are declared as input wire by default. Using input wire d, clk explicitly declares the inputs.

2fill in blank

medium

Complete the always block sensitivity list to trigger on the positive edge of the clock.

Verilog

always @([1]) begin
  q <= d;
end

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Anegedge clk

Bclk

Cd

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge clk which triggers on the falling edge.

Using just clk which triggers on any change.

The D flip-flop updates its output on the positive edge of the clock, so the sensitivity list should be posedge clk.

3fill in blank

hard

Fix the error in the assignment inside the always block to correctly update the output.

Verilog

always @(posedge clk) begin
  q [1] d;
end

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A<=

B=

C==

D+=

Attempts:

3 left

💡 Hint

Common Mistakes

Using blocking assignment = which can cause timing issues.

Using comparison operator == instead of assignment.

Non-blocking assignment <= is used inside clocked always blocks to update registers correctly.

4fill in blank

hard

Fill both blanks to add asynchronous reset to the D flip-flop.

Verilog

always @([1] or [2]) begin
  if (reset) q <= 0;
  else q <= d;
end

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Aposedge clk

Bnegedge reset

Cposedge reset

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using only clock edge without reset in sensitivity list.

Using wrong reset edge like posedge reset when reset is active low.

The always block triggers on the positive edge of the clock and the negative edge of the reset signal for asynchronous reset.

5fill in blank

hard

Fill all three blanks to complete the D flip-flop with synchronous reset and enable signal.

Verilog

always @(posedge clk) begin
  if ([1]) q <= 0;
  else if ([2]) q <= d;
  else q <= q;
end

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Areset

Benable

Cenable == 1

Dreset == 1

Attempts:

3 left

💡 Hint

Common Mistakes

Using asynchronous reset inside synchronous block.

Not checking enable condition properly.

The synchronous reset is checked first with reset == 1. Then the enable condition enable == 1 controls updating q. The reset is active high, so reset == 1 is used.