D flip-flop with clock edge in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the D flip-flop module with inputs and output.

Verilog

module d_flip_flop([1], output reg q);
  // input d, clk;
endmodule

Drag options to blanks, or click blank then click option'

Ainput wire d, clk

Boutput d, clk

Cinput reg d, clk

Dinput d, clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using output instead of input for inputs.

Declaring inputs as reg which is incorrect.

In Verilog, inputs are declared as input wire by default. Using input wire d, clk explicitly declares the inputs.

2fill in blank

medium

Complete the always block sensitivity list to trigger on the positive edge of the clock.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Anegedge clk

Bclk

Cd

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge clk which triggers on the falling edge.

Using just clk which triggers on any change.

The D flip-flop updates its output on the positive edge of the clock, so the sensitivity list should be posedge clk.

3fill in blank

hard

Fix the error in the assignment inside the always block to correctly update the output.

Verilog

always @(posedge clk) begin
  q [1] d;
end

Drag options to blanks, or click blank then click option'

A<=

B=

C==

D+=

Attempts:

3 left

💡 Hint

Common Mistakes

Using blocking assignment = which can cause timing issues.

Using comparison operator == instead of assignment.

Non-blocking assignment <= is used inside clocked always blocks to update registers correctly.

4fill in blank

hard

Fill both blanks to add asynchronous reset to the D flip-flop.

Verilog

always @([1] or [2]) begin
  if (reset) q <= 0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge reset

Cposedge reset

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using only clock edge without reset in sensitivity list.

Using wrong reset edge like posedge reset when reset is active low.

The always block triggers on the positive edge of the clock and the negative edge of the reset signal for asynchronous reset.

5fill in blank

hard

Fill all three blanks to complete the D flip-flop with synchronous reset and enable signal.

Verilog

always @(posedge clk) begin
  if ([1]) q <= 0;
  else if ([2]) q <= d;
  else q <= q;
end

Drag options to blanks, or click blank then click option'

Areset

Benable

Cenable == 1

Dreset == 1

Attempts:

3 left

💡 Hint

Common Mistakes

Using asynchronous reset inside synchronous block.

Not checking enable condition properly.

The synchronous reset is checked first with reset == 1. Then the enable condition enable == 1 controls updating q. The reset is active high, so reset == 1 is used.

Practice

1.

What does a D flip-flop do in a digital circuit?

easy

A. Stores the input value on the rising edge of the clock

B. Generates a clock signal

C. Performs arithmetic operations

D. Resets the circuit asynchronously

Solution

1. Step 1: Understand the role of a D flip-flop

   A D flip-flop captures and stores the input value (D) at a specific clock event.

2. Step 2: Identify the clock event

   It stores the value on the rising edge (positive edge) of the clock signal.

3. Final Answer:

   Stores the input value on the rising edge of the clock -> Option A

4. Quick Check:

   D flip-flop stores input on clock rising edge [OK]

Hint: Remember: D flip-flop stores data at clock's rising edge [OK]

Common Mistakes:

• Confusing D flip-flop with clock generator
• Thinking it performs calculations
• Assuming it resets asynchronously

2.

Which of the following is the correct Verilog syntax to trigger a D flip-flop on the rising edge of the clock clk?

easy

A. always @(negedge clk)

B. always @(posedge clk)

C. always @(clk)

D. always @(clk posedge)

Solution

1. Step 1: Recall the correct event control syntax

   Verilog uses posedge to detect the rising edge of a signal.

2. Step 2: Match syntax with clock signal

   The correct syntax to trigger on rising edge of clk is always @(posedge clk).

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge [OK]

Hint: Use 'posedge' for rising edge in always block [OK]

Common Mistakes:

• Using negedge instead of posedge
• Omitting posedge keyword
• Incorrect event control syntax

3.

What will be the output q after the following Verilog code runs for one clock cycle if d = 1 and initial q = 0?

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

medium

A. q remains 0

B. q toggles between 0 and 1

C. q becomes undefined

D. q becomes 1

Solution

1. Step 1: Understand the behavior on posedge clk

   On the rising edge of clk, the flip-flop assigns d to q.

2. Step 2: Apply given inputs

   Since d = 1 and initial q = 0, after the clock edge, q updates to 1.

3. Final Answer:

   q becomes 1 -> Option D

4. Quick Check:

   D input 1 stored at clock edge = q 1 [OK]

Hint: On clock rising edge, q copies d value [OK]

Common Mistakes:

• Assuming q changes immediately without clock edge
• Thinking q toggles automatically
• Ignoring initial value of q

4.

Identify the error in this D flip-flop Verilog code snippet:

module dff(input clk, input d, output reg q);
  always @(clk) begin
    q <= d;
  end
endmodule

medium

A. Missing sensitivity to clock edge, should use posedge

B. Output q should not be reg

C. Input d should be reg type

D. No error, code is correct

Solution

1. Step 1: Check sensitivity list

   The code uses always @(clk), which triggers on any change of clk, not just edges.

2. Step 2: Correct edge sensitivity

   For a D flip-flop, it must trigger only on the rising edge: always @(posedge clk).

3. Final Answer:

   Missing sensitivity to clock edge, should use posedge -> Option A

4. Quick Check:

   Flip-flop triggers on posedge clk only [OK]

Hint: Use posedge in always block for flip-flop [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing reg and wire for outputs
• Assuming inputs must be reg

5.

You want to design a D flip-flop that resets q to 0 asynchronously when rst is high. Which Verilog code snippet correctly implements this behavior?

module dff(input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

hard

A. The sensitivity list is missing negedge rst

B. Reset should be checked only on clock edge, not asynchronously

C. This code correctly implements asynchronous reset

D. q should be assigned with blocking assignment (=) inside always

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clock or rising edge of reset, enabling asynchronous reset.

2. Step 2: Check reset logic

   If reset is high, q is set to 0 immediately, else q follows d on clock edge.

3. Final Answer:

   This code correctly implements asynchronous reset -> Option C

4. Quick Check:

   Asynchronous reset uses posedge rst in sensitivity list [OK]

Hint: Add posedge rst in sensitivity list for async reset [OK]

Common Mistakes:

• Checking reset only on clock edge (synchronous reset)
• Using blocking assignment for sequential logic
• Missing reset in sensitivity list