D flip-flop with clock edge in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of D flip-flop on rising clock edge

What is the output q after the rising edge of the clock in this D flip-flop module?

Verilog

module dff(input wire clk, input wire d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

// Initial state: q = 0
// Inputs: clk rising edge, d = 1
// What is q after the clock edge?

A q = 1

B q = 0

C q toggles

D q holds previous value

💡 Hint

Remember, on the rising edge of the clock, the flip-flop captures the value of d.

The D flip-flop updates q to the value of d at the rising edge of clk. Since d is 1, q becomes 1.

❓ Predict Output

intermediate

Behavior of D flip-flop with asynchronous reset

Given this D flip-flop with asynchronous reset, what is the output q after reset is asserted low?

Verilog

module dff_async_reset(input wire clk, input wire reset, input wire d, output reg q);
  always @(posedge clk or negedge reset) begin
    if (!reset)
      q <= 0;
    else
      q <= d;
  end
endmodule

// Initial q unknown
// reset = 0 (asserted), d = 1
// What is q?

A q toggles

B q = 0

C q holds previous value

D q = 1

💡 Hint

Asynchronous reset forces q to 0 immediately when reset is low.

The asynchronous reset triggers on the negative edge of reset. When reset is 0, q is set to 0 regardless of clock or d.

🔧 Debug

advanced

Identify the error in this D flip-flop code

What error will this D flip-flop code cause when synthesized?

Verilog

module dff_error(input wire clk, input wire d, output reg q);
  always @(clk) begin
    if (clk == 1)
      q <= d;
  end
endmodule

A It causes a syntax error due to missing posedge

B It causes a runtime error

C It synthesizes correctly as a flip-flop

D It creates a latch instead of a flip-flop

💡 Hint

Check the sensitivity list and how the clock is used.

The sensitivity list uses clk level, not edge. This causes inferred latch behavior, not a proper flip-flop.

📝 Syntax

advanced

Syntax error in D flip-flop declaration

Which option contains a syntax error in this D flip-flop module?

Verilog

module dff_syntax(input wire clk, input wire d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

A module dff(input clk, input d, output reg q) always @(posedge clk) q <= d; endmodule

B module dff(input wire clk, input wire d, output reg q); always @(posedge clk) q <= d; endmodule

C module dff(input wire clk, input wire d, output reg q); always @(posedge clk) begin q <= d; end endmodule

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💡 Hint

Look for missing semicolons and missing begin/end blocks.

Option A misses semicolons and begin/end around the always block, causing syntax errors.

🚀 Application

expert

Number of clock cycles for output change in D flip-flop chain

Consider a chain of three D flip-flops connected in series, each clocked by the same clock signal. If the input d to the first flip-flop changes at clock cycle 0, after how many clock cycles will the output of the third flip-flop reflect this change?

A 1 clock cycle

B 2 clock cycles

C 3 clock cycles

D 4 clock cycles

💡 Hint

Each flip-flop updates its output on the rising edge of the clock, passing the value to the next flip-flop on the next clock cycle.

The first flip-flop captures the input at cycle 1, the second at cycle 2, and the third at cycle 3. So the third flip-flop output changes after 3 clock cycles.