D flip-flop with clock edge in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of D flip-flop on rising clock edge

What is the output q after the rising edge of the clock in this D flip-flop module?

Verilog

module dff(input wire clk, input wire d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

// Initial state: q = 0
// Inputs: clk rising edge, d = 1
// What is q after the clock edge?

A q = 1

B q = 0

C q toggles

D q holds previous value

💡 Hint

Remember, on the rising edge of the clock, the flip-flop captures the value of d.

The D flip-flop updates q to the value of d at the rising edge of clk. Since d is 1, q becomes 1.

❓ Predict Output

intermediate

Behavior of D flip-flop with asynchronous reset

Given this D flip-flop with asynchronous reset, what is the output q after reset is asserted low?

Verilog

module dff_async_reset(input wire clk, input wire reset, input wire d, output reg q);
  always @(posedge clk or negedge reset) begin
    if (!reset)
      q <= 0;
    else
      q <= d;
  end
endmodule

// Initial q unknown
// reset = 0 (asserted), d = 1
// What is q?

A q toggles

B q = 0

C q holds previous value

D q = 1

💡 Hint

Asynchronous reset forces q to 0 immediately when reset is low.

The asynchronous reset triggers on the negative edge of reset. When reset is 0, q is set to 0 regardless of clock or d.

🔧 Debug

advanced

Identify the error in this D flip-flop code

What error will this D flip-flop code cause when synthesized?

Verilog

module dff_error(input wire clk, input wire d, output reg q);
  always @(clk) begin
    if (clk == 1)
      q <= d;
  end
endmodule

A It causes a syntax error due to missing posedge

B It causes a runtime error

C It synthesizes correctly as a flip-flop

D It creates a latch instead of a flip-flop

💡 Hint

Check the sensitivity list and how the clock is used.

The sensitivity list uses clk level, not edge. This causes inferred latch behavior, not a proper flip-flop.

📝 Syntax

advanced

Syntax error in D flip-flop declaration

Which option contains a syntax error in this D flip-flop module?

Verilog

module dff_syntax(input wire clk, input wire d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

A module dff(input clk, input d, output reg q) always @(posedge clk) q <= d; endmodule

B module dff(input wire clk, input wire d, output reg q); always @(posedge clk) q <= d; endmodule

C module dff(input wire clk, input wire d, output reg q); always @(posedge clk) begin q <= d; end endmodule

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💡 Hint

Look for missing semicolons and missing begin/end blocks.

Option A misses semicolons and begin/end around the always block, causing syntax errors.

🚀 Application

expert

Number of clock cycles for output change in D flip-flop chain

Consider a chain of three D flip-flops connected in series, each clocked by the same clock signal. If the input d to the first flip-flop changes at clock cycle 0, after how many clock cycles will the output of the third flip-flop reflect this change?

A 1 clock cycle

B 2 clock cycles

C 3 clock cycles

D 4 clock cycles

💡 Hint

Each flip-flop updates its output on the rising edge of the clock, passing the value to the next flip-flop on the next clock cycle.

The first flip-flop captures the input at cycle 1, the second at cycle 2, and the third at cycle 3. So the third flip-flop output changes after 3 clock cycles.

Practice

1.

What does a D flip-flop do in a digital circuit?

easy

A. Stores the input value on the rising edge of the clock

B. Generates a clock signal

C. Performs arithmetic operations

D. Resets the circuit asynchronously

Solution

1. Step 1: Understand the role of a D flip-flop

   A D flip-flop captures and stores the input value (D) at a specific clock event.

2. Step 2: Identify the clock event

   It stores the value on the rising edge (positive edge) of the clock signal.

3. Final Answer:

   Stores the input value on the rising edge of the clock -> Option A

4. Quick Check:

   D flip-flop stores input on clock rising edge [OK]

Hint: Remember: D flip-flop stores data at clock's rising edge [OK]

Common Mistakes:

• Confusing D flip-flop with clock generator
• Thinking it performs calculations
• Assuming it resets asynchronously

2.

Which of the following is the correct Verilog syntax to trigger a D flip-flop on the rising edge of the clock clk?

easy

A. always @(negedge clk)

B. always @(posedge clk)

C. always @(clk)

D. always @(clk posedge)

Solution

1. Step 1: Recall the correct event control syntax

   Verilog uses posedge to detect the rising edge of a signal.

2. Step 2: Match syntax with clock signal

   The correct syntax to trigger on rising edge of clk is always @(posedge clk).

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge [OK]

Hint: Use 'posedge' for rising edge in always block [OK]

Common Mistakes:

• Using negedge instead of posedge
• Omitting posedge keyword
• Incorrect event control syntax

3.

What will be the output q after the following Verilog code runs for one clock cycle if d = 1 and initial q = 0?

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

medium

A. q remains 0

B. q toggles between 0 and 1

C. q becomes undefined

D. q becomes 1

Solution

1. Step 1: Understand the behavior on posedge clk

   On the rising edge of clk, the flip-flop assigns d to q.

2. Step 2: Apply given inputs

   Since d = 1 and initial q = 0, after the clock edge, q updates to 1.

3. Final Answer:

   q becomes 1 -> Option D

4. Quick Check:

   D input 1 stored at clock edge = q 1 [OK]

Hint: On clock rising edge, q copies d value [OK]

Common Mistakes:

• Assuming q changes immediately without clock edge
• Thinking q toggles automatically
• Ignoring initial value of q

4.

Identify the error in this D flip-flop Verilog code snippet:

module dff(input clk, input d, output reg q);
  always @(clk) begin
    q <= d;
  end
endmodule

medium

A. Missing sensitivity to clock edge, should use posedge

B. Output q should not be reg

C. Input d should be reg type

D. No error, code is correct

Solution

1. Step 1: Check sensitivity list

   The code uses always @(clk), which triggers on any change of clk, not just edges.

2. Step 2: Correct edge sensitivity

   For a D flip-flop, it must trigger only on the rising edge: always @(posedge clk).

3. Final Answer:

   Missing sensitivity to clock edge, should use posedge -> Option A

4. Quick Check:

   Flip-flop triggers on posedge clk only [OK]

Hint: Use posedge in always block for flip-flop [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing reg and wire for outputs
• Assuming inputs must be reg

5.

You want to design a D flip-flop that resets q to 0 asynchronously when rst is high. Which Verilog code snippet correctly implements this behavior?

module dff(input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

hard

A. The sensitivity list is missing negedge rst

B. Reset should be checked only on clock edge, not asynchronously

C. This code correctly implements asynchronous reset

D. q should be assigned with blocking assignment (=) inside always

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clock or rising edge of reset, enabling asynchronous reset.

2. Step 2: Check reset logic

   If reset is high, q is set to 0 immediately, else q follows d on clock edge.

3. Final Answer:

   This code correctly implements asynchronous reset -> Option C

4. Quick Check:

   Asynchronous reset uses posedge rst in sensitivity list [OK]

Hint: Add posedge rst in sensitivity list for async reset [OK]

Common Mistakes:

• Checking reset only on clock edge (synchronous reset)
• Using blocking assignment for sequential logic
• Missing reset in sensitivity list