Case statement for multiplexing in Verilog - Step-by-Step Execution

Concept Flow - Case statement for multiplexing

Start

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Read select input

↓

Case statement

↓

Case 0: Output input0

↓

Case 1: Output input1

↓

Case 2: Output input2

↓

Default: Output 0

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Output result

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End

The case statement reads the select input and chooses which input to send to output, like a traffic controller directing signals.

Execution Sample

Verilog

always @(*) begin
  case(sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    default: out = 0;
  endcase
end

This code picks one input (in0, in1, or in2) based on sel and sends it to out.

Execution Table

Step	sel	Case Condition	Action	out Value
1	2'b00	sel == 2'b00	out = in0	in0 value
2	2'b01	sel == 2'b01	out = in1	in1 value
3	2'b10	sel == 2'b10	out = in2	in2 value
4	2'b11	default case	out = 0	0

💡 All cases checked; output assigned based on sel value.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4
sel	undefined	2'b00	2'b01	2'b10	2'b11
out	undefined	in0 value	in1 value	in2 value	0

Key Moments - 3 Insights

Why does the output change only after the case matches the select input?

Because the case statement checks sel step-by-step and assigns out only when a matching case is found, as shown in execution_table rows 1-4.

What happens if sel has a value not listed in the cases?

The default case runs, assigning out = 0, ensuring output is always defined (see execution_table row 4).

Why do we use a case statement instead of multiple if-else statements?

Case statements are clearer and more efficient for selecting among many fixed options, as shown by the simple flow in concept_flow.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of out when sel is 2'b01?

A in2 value

B in0 value

C in1 value

D 0

💡 Hint

Check execution_table row 2 where sel == 2'b01 and out is assigned.

At which step does the default case assign out to 0?

A Step 1

B Step 4

C Step 3

D Step 2

💡 Hint

Look at execution_table row 4 where sel is 2'b11 and default case runs.

If sel changes from 2'b00 to 2'b10, how does out change according to variable_tracker?

A out changes from in0 value to in2 value

B out stays at in0 value

C out changes from in1 value to 0

D out changes from 0 to in1 value

💡 Hint

Check variable_tracker row for out between After Step 1 and After Step 3.

Concept Snapshot

Case statement syntax:
case(sel)
  value1: out = input1;
  value2: out = input2;
  default: out = 0;
endcase

It selects output based on sel value, like a switch directing traffic.

Full Transcript

This visual execution shows how a Verilog case statement works for multiplexing. The case reads the select input 'sel' and matches it to one of the cases. When a match is found, it assigns the corresponding input to the output 'out'. If no match is found, the default case assigns zero to 'out'. The execution table traces each step with sel values and output assignments. The variable tracker shows how 'sel' and 'out' change over time. Key moments clarify why output changes only on matching cases and the role of the default case. The quiz tests understanding of output values at different steps and how changes in sel affect out. This helps beginners see exactly how multiplexing works with case statements in Verilog.

Practice

1.

What is the main purpose of using a case statement in Verilog for multiplexing?

easy

A. To declare variables for storage

B. To create a loop that repeats operations

C. To define timing delays in the circuit

D. To select one input from many based on a selector signal

Solution

1. Step 1: Understand multiplexing concept

   Multiplexing means choosing one input out of many based on a selector signal.

2. Step 2: Role of case statement

   The case statement in Verilog is used to pick one input depending on the selector value.

3. Final Answer:

   To select one input from many based on a selector signal -> Option D

4. Quick Check:

   Multiplexer selection = case statement use [OK]

Hint: Case picks input based on selector signal [OK]

Common Mistakes:

• Confusing case with loops
• Using case for variable declaration
• Thinking case defines timing

2.

Which of the following is the correct syntax to start a case statement for a 2-bit selector sel in Verilog?

?

easy

A. case(sel) begin

B. case sel {

C. case(sel)

D. switch(sel) {

Solution

1. Step 1: Recall Verilog case syntax

   The correct syntax to start a case statement is case(expression) without extra keywords or braces.

2. Step 2: Check options

   case(sel) matches the correct syntax exactly: case(sel).

3. Final Answer:

   case(sel) -> Option C

4. Quick Check:

   Verilog case syntax = case(expression) [OK]

Hint: Use parentheses around selector in case [OK]

Common Mistakes:

• Adding 'begin' after case
• Using braces {} like other languages
• Using 'switch' instead of 'case'

3.

Given the following Verilog code, what is the value of out when sel = 2'b10?

module mux_example(input [1:0] sel, input a, b, c, d, output reg out);
  always @(*) begin
    case(sel)
      2'b00: out = a;
      2'b01: out = b;
      2'b10: out = c;
      default: out = d;
    endcase
  end
endmodule

medium

A. Value of input b

B. Value of input c

C. Value of input a

D. Value of input d

Solution

1. Step 1: Identify selector value

   The selector sel is 2'b10, which matches the third case.

2. Step 2: Match case to output

   For 2'b10, the output out is assigned the value of input c.

3. Final Answer:

   Value of input c -> Option B

4. Quick Check:

   sel=2'b10 selects c [OK]

Hint: Match selector bits to case labels [OK]

Common Mistakes:

• Choosing default instead of matching case
• Mixing up input variables
• Ignoring binary selector format

4.

Identify the error in this Verilog case statement used for multiplexing:

always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
  endcase
end

medium

A. Missing default case for unmatched selector values

B. Incorrect use of always block sensitivity list

C. Wrong assignment operator used

D. Selector signal sel is not declared

Solution

1. Step 1: Check case completeness

   The case statement covers 2'b00, 2'b01, and 2'b10 but misses 2'b11.

2. Step 2: Importance of default case

   Without a default case, the output out may hold previous value or be undefined for unmatched selectors.

3. Final Answer:

   Missing default case for unmatched selector values -> Option A

4. Quick Check:

   Always include default in case [OK]

Hint: Always add default case in multiplexers [OK]

Common Mistakes:

• Forgetting default case
• Using wrong sensitivity list (@posedge instead of @(*) )
• Using '=' instead of '<=' in combinational logic

5.

You want to design a 4-to-1 multiplexer using a case statement in Verilog. Which of the following code snippets correctly implements this with inputs a, b, c, d, selector sel, and output out?

?

hard

A. always @(*) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
default: out = 1'b0;
endcase
end

B. always @(sel) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
default: out = d;
endcase
end

C. always @(*) begin
if(sel == 2'b00) out = a;
else if(sel == 2'b01) out = b;
else if(sel == 2'b10) out = c;
else out = d;
end

D. always @(*) begin
case(sel)
0: out = a;
1: out = b;
2: out = c;
3: out = d;
endcase
end

Solution

1. Step 1: Check sensitivity list

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end uses always @(*), which is correct for combinational logic multiplexers.

2. Step 2: Verify case labels and default

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end covers all 4 selector values (2'b00 to 2'b11) and includes a default case to avoid latches.

3. Step 3: Compare other options

   always @(sel) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; default: out = d; endcase end misses 2'b11 case explicitly and uses always @(sel) which is less recommended. always @(*) begin if(sel == 2'b00) out = a; else if(sel == 2'b01) out = b; else if(sel == 2'b10) out = c; else out = d; end uses if-else, not case. always @(*) begin case(sel) 0: out = a; 1: out = b; 2: out = c; 3: out = d; endcase end uses decimal labels without binary format and misses default.

4. Final Answer:

   Option A code snippet -> Option A

5. Quick Check:

   Complete case with default and always @(*) = always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end [OK]

Hint: Use always @(*) and include default case [OK]

Common Mistakes:

• Omitting default case
• Using incomplete case labels
• Wrong sensitivity list
• Mixing if-else with case question