Case statement for multiplexing in Verilog - Step-by-Step Execution

Concept Flow - Case statement for multiplexing

Start

↓

Read select input

↓

Case statement

↓

Case 0: Output input0

↓

Case 1: Output input1

↓

Case 2: Output input2

↓

Default: Output 0

↓

Output result

↓

End

The case statement reads the select input and chooses which input to send to output, like a traffic controller directing signals.

Execution Sample

Verilog

always @(*) begin
  case(sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    default: out = 0;
  endcase
end

This code picks one input (in0, in1, or in2) based on sel and sends it to out.

Execution Table

Step	sel	Case Condition	Action	out Value
1	2'b00	sel == 2'b00	out = in0	in0 value
2	2'b01	sel == 2'b01	out = in1	in1 value
3	2'b10	sel == 2'b10	out = in2	in2 value
4	2'b11	default case	out = 0	0

💡 All cases checked; output assigned based on sel value.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4
sel	undefined	2'b00	2'b01	2'b10	2'b11
out	undefined	in0 value	in1 value	in2 value	0

Key Moments - 3 Insights

Why does the output change only after the case matches the select input?

Because the case statement checks sel step-by-step and assigns out only when a matching case is found, as shown in execution_table rows 1-4.

What happens if sel has a value not listed in the cases?

The default case runs, assigning out = 0, ensuring output is always defined (see execution_table row 4).

Why do we use a case statement instead of multiple if-else statements?

Case statements are clearer and more efficient for selecting among many fixed options, as shown by the simple flow in concept_flow.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of out when sel is 2'b01?

A in2 value

B in0 value

C in1 value

D 0

💡 Hint

Check execution_table row 2 where sel == 2'b01 and out is assigned.

At which step does the default case assign out to 0?

A Step 1

B Step 4

C Step 3

D Step 2

💡 Hint

Look at execution_table row 4 where sel is 2'b11 and default case runs.

If sel changes from 2'b00 to 2'b10, how does out change according to variable_tracker?

A out changes from in0 value to in2 value

B out stays at in0 value

C out changes from in1 value to 0

D out changes from 0 to in1 value

💡 Hint

Check variable_tracker row for out between After Step 1 and After Step 3.

Concept Snapshot

Case statement syntax:
case(sel)
  value1: out = input1;
  value2: out = input2;
  default: out = 0;
endcase

It selects output based on sel value, like a switch directing traffic.

Full Transcript

This visual execution shows how a Verilog case statement works for multiplexing. The case reads the select input 'sel' and matches it to one of the cases. When a match is found, it assigns the corresponding input to the output 'out'. If no match is found, the default case assigns zero to 'out'. The execution table traces each step with sel values and output assignments. The variable tracker shows how 'sel' and 'out' change over time. Key moments clarify why output changes only on matching cases and the role of the default case. The quiz tests understanding of output values at different steps and how changes in sel affect out. This helps beginners see exactly how multiplexing works with case statements in Verilog.