Case statement for multiplexing in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of a case statement in Verilog multiplexing?

A case statement selects one output from many inputs based on a selector value, making it ideal for multiplexing signals.

beginner

How does a 2-to-1 multiplexer work using a case statement?

It uses a 1-bit selector to choose between two inputs. The case checks the selector and outputs the corresponding input.

intermediate

Write a simple Verilog case statement for a 4-to-1 multiplexer.

Example:

always @(*) begin
  case(sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    2'b11: out = in3;
    default: out = 1'b0;
  endcase
end

intermediate

Why is it important to include a default case in a Verilog case statement?

The default case ensures the output is defined for all selector values, preventing latches and unintended behavior.

advanced

What happens if a case statement in Verilog does not cover all possible selector values?

If some selector values are not covered and no default is provided, the output may become undefined or cause latches, leading to unpredictable results.

In a Verilog case statement for multiplexing, what does the selector signal do?

A Controls the clock speed

B Chooses which input to send to the output

C Resets the output

D Generates random values

The selector signal decides which input is passed to the output in a multiplexer.

What is the minimum number of bits needed for the selector to choose among 8 inputs?

A 3 bits

B 8 bits

C 4 bits

D 2 bits

3 bits can represent 8 different values (0 to 7), enough to select among 8 inputs.

What keyword is used in Verilog to handle all unspecified cases in a case statement?

A else

B otherwise

C catch

D default

The default keyword covers all cases not explicitly listed in the case statement.

What could happen if a case statement misses some selector values and has no default case?

A The output may become undefined or cause latches

B The output will always be zero

C The program will not compile

D The selector will automatically reset

Missing cases without a default can cause unintended latches or undefined outputs.

Which of the following is a correct way to write a 2-to-1 multiplexer using a case statement?

A case(sel) 0: out = in0; 1: out = in1; endcase

B case(sel) 2'b00: out = in0; 2'b01: out = in1; endcase

C case(sel) 1'b0: out = in0; 1'b1: out = in1; endcase

D case(sel) 1: out = in0; 0: out = in1; endcase

For a 1-bit selector, values 1'b0 and 1'b1 select inputs in a 2-to-1 mux.

Explain how a case statement is used to implement a multiplexer in Verilog.

Think about how the selector chooses one input to send to the output.

Describe why including a default case in a Verilog case statement is important for multiplexers.

Consider what happens if the selector has a value not listed in the cases.

Practice

1.

What is the main purpose of using a case statement in Verilog for multiplexing?

easy

A. To declare variables for storage

B. To create a loop that repeats operations

C. To define timing delays in the circuit

D. To select one input from many based on a selector signal

Solution

1. Step 1: Understand multiplexing concept

   Multiplexing means choosing one input out of many based on a selector signal.

2. Step 2: Role of case statement

   The case statement in Verilog is used to pick one input depending on the selector value.

3. Final Answer:

   To select one input from many based on a selector signal -> Option D

4. Quick Check:

   Multiplexer selection = case statement use [OK]

Hint: Case picks input based on selector signal [OK]

Common Mistakes:

• Confusing case with loops
• Using case for variable declaration
• Thinking case defines timing

2.

Which of the following is the correct syntax to start a case statement for a 2-bit selector sel in Verilog?

?

easy

A. case(sel) begin

B. case sel {

C. case(sel)

D. switch(sel) {

Solution

1. Step 1: Recall Verilog case syntax

   The correct syntax to start a case statement is case(expression) without extra keywords or braces.

2. Step 2: Check options

   case(sel) matches the correct syntax exactly: case(sel).

3. Final Answer:

   case(sel) -> Option C

4. Quick Check:

   Verilog case syntax = case(expression) [OK]

Hint: Use parentheses around selector in case [OK]

Common Mistakes:

• Adding 'begin' after case
• Using braces {} like other languages
• Using 'switch' instead of 'case'

3.

Given the following Verilog code, what is the value of out when sel = 2'b10?

module mux_example(input [1:0] sel, input a, b, c, d, output reg out);
  always @(*) begin
    case(sel)
      2'b00: out = a;
      2'b01: out = b;
      2'b10: out = c;
      default: out = d;
    endcase
  end
endmodule

medium

A. Value of input b

B. Value of input c

C. Value of input a

D. Value of input d

Solution

1. Step 1: Identify selector value

   The selector sel is 2'b10, which matches the third case.

2. Step 2: Match case to output

   For 2'b10, the output out is assigned the value of input c.

3. Final Answer:

   Value of input c -> Option B

4. Quick Check:

   sel=2'b10 selects c [OK]

Hint: Match selector bits to case labels [OK]

Common Mistakes:

• Choosing default instead of matching case
• Mixing up input variables
• Ignoring binary selector format

4.

Identify the error in this Verilog case statement used for multiplexing:

always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
  endcase
end

medium

A. Missing default case for unmatched selector values

B. Incorrect use of always block sensitivity list

C. Wrong assignment operator used

D. Selector signal sel is not declared

Solution

1. Step 1: Check case completeness

   The case statement covers 2'b00, 2'b01, and 2'b10 but misses 2'b11.

2. Step 2: Importance of default case

   Without a default case, the output out may hold previous value or be undefined for unmatched selectors.

3. Final Answer:

   Missing default case for unmatched selector values -> Option A

4. Quick Check:

   Always include default in case [OK]

Hint: Always add default case in multiplexers [OK]

Common Mistakes:

• Forgetting default case
• Using wrong sensitivity list (@posedge instead of @(*) )
• Using '=' instead of '<=' in combinational logic

5.

You want to design a 4-to-1 multiplexer using a case statement in Verilog. Which of the following code snippets correctly implements this with inputs a, b, c, d, selector sel, and output out?

?

hard

A. always @(*) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
default: out = 1'b0;
endcase
end

B. always @(sel) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
default: out = d;
endcase
end

C. always @(*) begin
if(sel == 2'b00) out = a;
else if(sel == 2'b01) out = b;
else if(sel == 2'b10) out = c;
else out = d;
end

D. always @(*) begin
case(sel)
0: out = a;
1: out = b;
2: out = c;
3: out = d;
endcase
end

Solution

1. Step 1: Check sensitivity list

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end uses always @(*), which is correct for combinational logic multiplexers.

2. Step 2: Verify case labels and default

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end covers all 4 selector values (2'b00 to 2'b11) and includes a default case to avoid latches.

3. Step 3: Compare other options

   always @(sel) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; default: out = d; endcase end misses 2'b11 case explicitly and uses always @(sel) which is less recommended. always @(*) begin if(sel == 2'b00) out = a; else if(sel == 2'b01) out = b; else if(sel == 2'b10) out = c; else out = d; end uses if-else, not case. always @(*) begin case(sel) 0: out = a; 1: out = b; 2: out = c; 3: out = d; endcase end uses decimal labels without binary format and misses default.

4. Final Answer:

   Option A code snippet -> Option A

5. Quick Check:

   Complete case with default and always @(*) = always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end [OK]

Hint: Use always @(*) and include default case [OK]

Common Mistakes:

• Omitting default case
• Using incomplete case labels
• Wrong sensitivity list
• Mixing if-else with case question