Case statement for multiplexing in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of a case statement in Verilog multiplexing?

A case statement selects one output from many inputs based on a selector value, making it ideal for multiplexing signals.

beginner

How does a 2-to-1 multiplexer work using a case statement?

It uses a 1-bit selector to choose between two inputs. The case checks the selector and outputs the corresponding input.

intermediate

Write a simple Verilog case statement for a 4-to-1 multiplexer.

Example:

always @(*) begin
  case(sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    2'b11: out = in3;
    default: out = 1'b0;
  endcase
end

intermediate

Why is it important to include a default case in a Verilog case statement?

The default case ensures the output is defined for all selector values, preventing latches and unintended behavior.

advanced

What happens if a case statement in Verilog does not cover all possible selector values?

If some selector values are not covered and no default is provided, the output may become undefined or cause latches, leading to unpredictable results.

In a Verilog case statement for multiplexing, what does the selector signal do?

A Controls the clock speed

B Chooses which input to send to the output

C Resets the output

D Generates random values

The selector signal decides which input is passed to the output in a multiplexer.

What is the minimum number of bits needed for the selector to choose among 8 inputs?

A 3 bits

B 8 bits

C 4 bits

D 2 bits

3 bits can represent 8 different values (0 to 7), enough to select among 8 inputs.

What keyword is used in Verilog to handle all unspecified cases in a case statement?

A else

B otherwise

C catch

D default

The default keyword covers all cases not explicitly listed in the case statement.

What could happen if a case statement misses some selector values and has no default case?

A The output may become undefined or cause latches

B The output will always be zero

C The program will not compile

D The selector will automatically reset

Missing cases without a default can cause unintended latches or undefined outputs.

Which of the following is a correct way to write a 2-to-1 multiplexer using a case statement?

A case(sel) 0: out = in0; 1: out = in1; endcase

B case(sel) 2'b00: out = in0; 2'b01: out = in1; endcase

C case(sel) 1'b0: out = in0; 1'b1: out = in1; endcase

D case(sel) 1: out = in0; 0: out = in1; endcase

For a 1-bit selector, values 1'b0 and 1'b1 select inputs in a 2-to-1 mux.

Explain how a case statement is used to implement a multiplexer in Verilog.

Think about how the selector chooses one input to send to the output.

Describe why including a default case in a Verilog case statement is important for multiplexers.

Consider what happens if the selector has a value not listed in the cases.