Case statement for multiplexing in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to assign output based on select signal using a case statement.

Verilog

always @(*) begin
  case(sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    default: out = [1];
  endcase
end

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A1'b0

Bin3

C1'b1

Dsel

Attempts:

3 left

💡 Hint

Common Mistakes

Using an undefined signal in the default case.

Forgetting the default case causing latches.

The default case assigns a safe default value, usually 0, to the output.

2fill in blank

medium

Complete the case statement to select the correct input based on 2-bit select signal.

Verilog

always @(*) begin
  case([1])
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    2'b11: out = in3;
  endcase
end

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Aclk

Bout

Cin0

Dsel

Attempts:

3 left

💡 Hint

Common Mistakes

Using output or input signals as the case expression.

Using clock signal instead of select signal.

The case statement uses the select signal to choose which input to assign to output.

3fill in blank

hard

Fix the error in the case statement to correctly assign output based on select signal.

Verilog

always @(*) begin
  case(sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    2'b11: out = in3;
    default: out = [1];
  endcase
end

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A1'b0

Bsel

C1'bx

Din4

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning an undefined input in default case.

Using select signal as default output.

The default case should assign a known safe value like 0 to avoid latches and unknown states.

4fill in blank

hard

Fill both blanks to complete the case statement for a 4-to-1 multiplexer.

Verilog

always @(*) begin
  case([1])
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    2'b11: out = in3;
    default: out = [2];
  endcase
end

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Asel

B1'b0

C1'b1

Din4

Attempts:

3 left

💡 Hint

Common Mistakes

Using input signals or constants as case expression.

Assigning undefined signals in default case.

The case expression is the select signal, and the default output is zero to avoid latches.

5fill in blank

hard

Fill all three blanks to complete the case statement for a 4-input multiplexer with default output zero.

Verilog

always @(*) begin
  case([1])
    2'b00: out = [2];
    2'b01: out = [3];
    2'b10: out = in2;
    2'b11: out = in3;
    default: out = 1'b0;
  endcase
end

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Asel

Bin0

Cin1

Din4

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing input signals in wrong case branches.

Using wrong variable as case expression.

The case expression is the select signal. For select 00 and 01, output is in0 and in1 respectively.