Case statement for multiplexing in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-to-1 Multiplexer Using Case Statement

What is the output y of this Verilog code when sel = 2'b10?

Verilog

module mux4to1(input [1:0] sel, input [3:0] d, output reg y);
  always @(*) begin
    case(sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      2'b11: y = d[3];
      default: y = 1'b0;
    endcase
  end
endmodule

// Inputs: sel = 2'b10, d = 4'b1011

A y = 1

B y = 0

C y = 1'bz (high impedance)

D y = 2'b10

💡 Hint

Look at which bit of d is selected by sel = 2'b10.

The case statement selects d[2] when sel is 2'b10. Given d = 4'b1011, bits are indexed from right to left: d[0]=1, d[1]=1, d[2]=0, d[3]=1. So d[2] is 0. The output y is assigned 0.

❓ Predict Output

intermediate

Behavior of Case Statement with Default in Multiplexer

What will be the output y if sel = 2'b11 and d = 4'b0101 in this Verilog code?

Verilog

module mux4to1(input [1:0] sel, input [3:0] d, output reg y);
  always @(*) begin
    case(sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      default: y = 1'b0;
    endcase
  end
endmodule

A y = 0

B y = 1

C y = d[3]

D y = 1'bx (unknown)

💡 Hint

Check what the default case does when sel is not explicitly matched.

The case statement does not have a case for 2'b11, so it uses the default case which assigns y = 1'b0. Therefore, output is 0 regardless of d.

🔧 Debug

advanced

Identify the Error in Multiplexer Case Statement

What error will this Verilog code produce when synthesized or simulated?

Verilog

module mux4to1(input [1:0] sel, input [3:0] d, output reg y);
  always @(*) begin
    case(sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      2'b11: y = d[3];
    endcase
  end
endmodule

A Type mismatch error between y and d bits

B Syntax error: missing parentheses around case expression

C No error, code works fine

D Latch inferred due to missing default case

💡 Hint

Recall the exact syntax for a case statement in Verilog.

Because there is no default case and not all possible values of sel are covered, a latch may be inferred to hold the previous value of y when sel is outside the specified cases.

📝 Syntax

advanced

Syntax Error in Case Statement for Multiplexer

Which option contains the correct syntax for the case statement in Verilog?

Verilog

always @(*) begin
  case(sel)
    2'b00: y = d[0];
    2'b01 y = d[1];
    2'b10: y = d[2];
    2'b11: y = d[3];
  endcase
end

A case(sel) 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; endcase

B case sel ( 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; ) endcase

C case(sel): 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; endcase

D case(sel) 2'b00 y = d[0]; 2'b01 y = d[1]; 2'b10 y = d[2]; 2'b11 y = d[3]; endcase

💡 Hint

Check for colons after each case label and correct case statement syntax.

Option A uses correct syntax: case(expression) with colons after each case label. Other options have syntax errors like missing colons, wrong parentheses, or misplaced colons.

🚀 Application

expert

Number of Output Changes in a 3-to-8 Decoder Using Case Statement

Consider a 3-to-8 decoder implemented with a case statement on a 3-bit input sel. How many output lines will be set to 1 for any single input value?

Verilog

module decoder3to8(input [2:0] sel, output reg [7:0] out);
  always @(*) begin
    out = 8'b00000000;
    case(sel)
      3'b000: out[0] = 1'b1;
      3'b001: out[1] = 1'b1;
      3'b010: out[2] = 1'b1;
      3'b011: out[3] = 1'b1;
      3'b100: out[4] = 1'b1;
      3'b101: out[5] = 1'b1;
      3'b110: out[6] = 1'b1;
      3'b111: out[7] = 1'b1;
    endcase
  end
endmodule

A All output bits are set to 1

B Two output bits are set to 1

C Exactly one output bit is set to 1

D No output bits are set to 1

💡 Hint

Look at how the output out is assigned before and inside the case statement.

The output out is first cleared to all zeros. Then exactly one bit corresponding to the input sel is set to 1. So for any input, only one output bit is high.