Case statement for multiplexing in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-to-1 Multiplexer Using Case Statement

What is the output y of this Verilog code when sel = 2'b10?

Verilog

module mux4to1(input [1:0] sel, input [3:0] d, output reg y);
  always @(*) begin
    case(sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      2'b11: y = d[3];
      default: y = 1'b0;
    endcase
  end
endmodule

// Inputs: sel = 2'b10, d = 4'b1011

A y = 1

B y = 0

C y = 1'bz (high impedance)

D y = 2'b10

💡 Hint

Look at which bit of d is selected by sel = 2'b10.

The case statement selects d[2] when sel is 2'b10. Given d = 4'b1011, bits are indexed from right to left: d[0]=1, d[1]=1, d[2]=0, d[3]=1. So d[2] is 0. The output y is assigned 0.

❓ Predict Output

intermediate

Behavior of Case Statement with Default in Multiplexer

What will be the output y if sel = 2'b11 and d = 4'b0101 in this Verilog code?

Verilog

module mux4to1(input [1:0] sel, input [3:0] d, output reg y);
  always @(*) begin
    case(sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      default: y = 1'b0;
    endcase
  end
endmodule

A y = 0

B y = 1

C y = d[3]

D y = 1'bx (unknown)

💡 Hint

Check what the default case does when sel is not explicitly matched.

The case statement does not have a case for 2'b11, so it uses the default case which assigns y = 1'b0. Therefore, output is 0 regardless of d.

🔧 Debug

advanced

Identify the Error in Multiplexer Case Statement

What error will this Verilog code produce when synthesized or simulated?

Verilog

module mux4to1(input [1:0] sel, input [3:0] d, output reg y);
  always @(*) begin
    case(sel)
      2'b00: y = d[0];
      2'b01: y = d[1];
      2'b10: y = d[2];
      2'b11: y = d[3];
    endcase
  end
endmodule

A Type mismatch error between y and d bits

B Syntax error: missing parentheses around case expression

C No error, code works fine

D Latch inferred due to missing default case

💡 Hint

Recall the exact syntax for a case statement in Verilog.

Because there is no default case and not all possible values of sel are covered, a latch may be inferred to hold the previous value of y when sel is outside the specified cases.

📝 Syntax

advanced

Syntax Error in Case Statement for Multiplexer

Which option contains the correct syntax for the case statement in Verilog?

Verilog

always @(*) begin
  case(sel)
    2'b00: y = d[0];
    2'b01 y = d[1];
    2'b10: y = d[2];
    2'b11: y = d[3];
  endcase
end

A case(sel) 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; endcase

B case sel ( 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; ) endcase

C case(sel): 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; endcase

D case(sel) 2'b00 y = d[0]; 2'b01 y = d[1]; 2'b10 y = d[2]; 2'b11 y = d[3]; endcase

💡 Hint

Check for colons after each case label and correct case statement syntax.

Option A uses correct syntax: case(expression) with colons after each case label. Other options have syntax errors like missing colons, wrong parentheses, or misplaced colons.

🚀 Application

expert

Number of Output Changes in a 3-to-8 Decoder Using Case Statement

Consider a 3-to-8 decoder implemented with a case statement on a 3-bit input sel. How many output lines will be set to 1 for any single input value?

Verilog

module decoder3to8(input [2:0] sel, output reg [7:0] out);
  always @(*) begin
    out = 8'b00000000;
    case(sel)
      3'b000: out[0] = 1'b1;
      3'b001: out[1] = 1'b1;
      3'b010: out[2] = 1'b1;
      3'b011: out[3] = 1'b1;
      3'b100: out[4] = 1'b1;
      3'b101: out[5] = 1'b1;
      3'b110: out[6] = 1'b1;
      3'b111: out[7] = 1'b1;
    endcase
  end
endmodule

A All output bits are set to 1

B Two output bits are set to 1

C Exactly one output bit is set to 1

D No output bits are set to 1

💡 Hint

Look at how the output out is assigned before and inside the case statement.

The output out is first cleared to all zeros. Then exactly one bit corresponding to the input sel is set to 1. So for any input, only one output bit is high.

Practice

1.

What is the main purpose of using a case statement in Verilog for multiplexing?

easy

A. To declare variables for storage

B. To create a loop that repeats operations

C. To define timing delays in the circuit

D. To select one input from many based on a selector signal

Solution

1. Step 1: Understand multiplexing concept

   Multiplexing means choosing one input out of many based on a selector signal.

2. Step 2: Role of case statement

   The case statement in Verilog is used to pick one input depending on the selector value.

3. Final Answer:

   To select one input from many based on a selector signal -> Option D

4. Quick Check:

   Multiplexer selection = case statement use [OK]

Hint: Case picks input based on selector signal [OK]

Common Mistakes:

• Confusing case with loops
• Using case for variable declaration
• Thinking case defines timing

2.

Which of the following is the correct syntax to start a case statement for a 2-bit selector sel in Verilog?

?

easy

A. case(sel) begin

B. case sel {

C. case(sel)

D. switch(sel) {

Solution

1. Step 1: Recall Verilog case syntax

   The correct syntax to start a case statement is case(expression) without extra keywords or braces.

2. Step 2: Check options

   case(sel) matches the correct syntax exactly: case(sel).

3. Final Answer:

   case(sel) -> Option C

4. Quick Check:

   Verilog case syntax = case(expression) [OK]

Hint: Use parentheses around selector in case [OK]

Common Mistakes:

• Adding 'begin' after case
• Using braces {} like other languages
• Using 'switch' instead of 'case'

3.

Given the following Verilog code, what is the value of out when sel = 2'b10?

module mux_example(input [1:0] sel, input a, b, c, d, output reg out);
  always @(*) begin
    case(sel)
      2'b00: out = a;
      2'b01: out = b;
      2'b10: out = c;
      default: out = d;
    endcase
  end
endmodule

medium

A. Value of input b

B. Value of input c

C. Value of input a

D. Value of input d

Solution

1. Step 1: Identify selector value

   The selector sel is 2'b10, which matches the third case.

2. Step 2: Match case to output

   For 2'b10, the output out is assigned the value of input c.

3. Final Answer:

   Value of input c -> Option B

4. Quick Check:

   sel=2'b10 selects c [OK]

Hint: Match selector bits to case labels [OK]

Common Mistakes:

• Choosing default instead of matching case
• Mixing up input variables
• Ignoring binary selector format

4.

Identify the error in this Verilog case statement used for multiplexing:

always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
  endcase
end

medium

A. Missing default case for unmatched selector values

B. Incorrect use of always block sensitivity list

C. Wrong assignment operator used

D. Selector signal sel is not declared

Solution

1. Step 1: Check case completeness

   The case statement covers 2'b00, 2'b01, and 2'b10 but misses 2'b11.

2. Step 2: Importance of default case

   Without a default case, the output out may hold previous value or be undefined for unmatched selectors.

3. Final Answer:

   Missing default case for unmatched selector values -> Option A

4. Quick Check:

   Always include default in case [OK]

Hint: Always add default case in multiplexers [OK]

Common Mistakes:

• Forgetting default case
• Using wrong sensitivity list (@posedge instead of @(*) )
• Using '=' instead of '<=' in combinational logic

5.

You want to design a 4-to-1 multiplexer using a case statement in Verilog. Which of the following code snippets correctly implements this with inputs a, b, c, d, selector sel, and output out?

?

hard

A. always @(*) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
default: out = 1'b0;
endcase
end

B. always @(sel) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
default: out = d;
endcase
end

C. always @(*) begin
if(sel == 2'b00) out = a;
else if(sel == 2'b01) out = b;
else if(sel == 2'b10) out = c;
else out = d;
end

D. always @(*) begin
case(sel)
0: out = a;
1: out = b;
2: out = c;
3: out = d;
endcase
end

Solution

1. Step 1: Check sensitivity list

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end uses always @(*), which is correct for combinational logic multiplexers.

2. Step 2: Verify case labels and default

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end covers all 4 selector values (2'b00 to 2'b11) and includes a default case to avoid latches.

3. Step 3: Compare other options

   always @(sel) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; default: out = d; endcase end misses 2'b11 case explicitly and uses always @(sel) which is less recommended. always @(*) begin if(sel == 2'b00) out = a; else if(sel == 2'b01) out = b; else if(sel == 2'b10) out = c; else out = d; end uses if-else, not case. always @(*) begin case(sel) 0: out = a; 1: out = b; 2: out = c; 3: out = d; endcase end uses decimal labels without binary format and misses default.

4. Final Answer:

   Option A code snippet -> Option A

5. Quick Check:

   Complete case with default and always @(*) = always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end [OK]

Hint: Use always @(*) and include default case [OK]

Common Mistakes:

• Omitting default case
• Using incomplete case labels
• Wrong sensitivity list
• Mixing if-else with case question