Case statement for multiplexing in Verilog - Mini Project: Build & Apply

Case Statement for Multiplexing in Verilog

📖 Scenario: You are designing a simple digital circuit that selects one of four 4-bit input signals based on a 2-bit selector signal. This is a common task in digital electronics called multiplexing.

🎯 Goal: Build a Verilog module that uses a case statement to select one of four 4-bit inputs and output it based on a 2-bit selector input.

📋 What You'll Learn

Create a Verilog module named mux4to1 with inputs and output as specified

Use a case statement inside an always block to implement the multiplexing logic

The module should have four 4-bit inputs named in0, in1, in2, in3

The module should have a 2-bit input named sel to select which input to output

The module should have a 4-bit output named out that reflects the selected input

💡 Why This Matters

🌍 Real World

Multiplexers are used in digital circuits to select one data source from many, saving hardware and routing signals efficiently.

💼 Career

Understanding multiplexers and case statements is essential for hardware design engineers and FPGA developers working with Verilog or VHDL.

1

Create the module and inputs/outputs

Write a Verilog module named mux4to1 with four 4-bit inputs called in0, in1, in2, in3, a 2-bit input called sel, and a 4-bit output called out. Declare out as reg.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

// Your code here

endmodule

Hint

Remember to declare out as reg because it will be assigned inside an always block.

2

Add the always block with selector

Inside the mux4to1 module, add an always block that is sensitive to changes in sel, in0, in1, in2, and in3.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

always @ (sel or in0 or in1 or in2 or in3) begin
    // Your code here
end

endmodule

Hint

The always block should react to changes in the selector and all inputs.

3

Implement the case statement for multiplexing

Inside the always block, write a case statement on sel that assigns out to in0 when sel is 0, in1 when sel is 1, in2 when sel is 2, and in3 when sel is 3. Include a default case that assigns out to 4'b0000.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

always @ (sel or in0 or in1 or in2 or in3) begin
    case (sel)
        // Your code here
    endcase
end

endmodule

Hint

Use binary values for sel cases and assign out accordingly.

4

Test the module output

Write a testbench module named test_mux4to1 that instantiates mux4to1. Assign in0 = 4'b0001, in1 = 4'b0010, in2 = 4'b0100, in3 = 4'b1000. Change sel from 0 to 3 in steps, and use $display to print sel and out. Run the testbench to show the output.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

always @ (sel or in0 or in1 or in2 or in3) begin
    case (sel)
        2'b00: out = in0;
        2'b01: out = in1;
        2'b10: out = in2;
        2'b11: out = in3;
        default: out = 4'b0000;
    endcase
end

endmodule

module test_mux4to1;
    reg [3:0] in0, in1, in2, in3;
    reg [1:0] sel;
    wire [3:0] out;

    mux4to1 uut(.in0(in0), .in1(in1), .in2(in2), .in3(in3), .sel(sel), .out(out));

    initial begin
        // Your code here
    end
endmodule

Hint

Assign the inputs with the given values, change sel step by step, wait a little with #10, and print the values using $display.

Practice

1.

What is the main purpose of using a case statement in Verilog for multiplexing?

easy

A. To declare variables for storage

B. To create a loop that repeats operations

C. To define timing delays in the circuit

D. To select one input from many based on a selector signal

Solution

1. Step 1: Understand multiplexing concept

   Multiplexing means choosing one input out of many based on a selector signal.

2. Step 2: Role of case statement

   The case statement in Verilog is used to pick one input depending on the selector value.

3. Final Answer:

   To select one input from many based on a selector signal -> Option D

4. Quick Check:

   Multiplexer selection = case statement use [OK]

Hint: Case picks input based on selector signal [OK]

Common Mistakes:

• Confusing case with loops
• Using case for variable declaration
• Thinking case defines timing

2.

Which of the following is the correct syntax to start a case statement for a 2-bit selector sel in Verilog?

?

easy

A. case(sel) begin

B. case sel {

C. case(sel)

D. switch(sel) {

Solution

1. Step 1: Recall Verilog case syntax

   The correct syntax to start a case statement is case(expression) without extra keywords or braces.

2. Step 2: Check options

   case(sel) matches the correct syntax exactly: case(sel).

3. Final Answer:

   case(sel) -> Option C

4. Quick Check:

   Verilog case syntax = case(expression) [OK]

Hint: Use parentheses around selector in case [OK]

Common Mistakes:

• Adding 'begin' after case
• Using braces {} like other languages
• Using 'switch' instead of 'case'

3.

Given the following Verilog code, what is the value of out when sel = 2'b10?

module mux_example(input [1:0] sel, input a, b, c, d, output reg out);
  always @(*) begin
    case(sel)
      2'b00: out = a;
      2'b01: out = b;
      2'b10: out = c;
      default: out = d;
    endcase
  end
endmodule

medium

A. Value of input b

B. Value of input c

C. Value of input a

D. Value of input d

Solution

1. Step 1: Identify selector value

   The selector sel is 2'b10, which matches the third case.

2. Step 2: Match case to output

   For 2'b10, the output out is assigned the value of input c.

3. Final Answer:

   Value of input c -> Option B

4. Quick Check:

   sel=2'b10 selects c [OK]

Hint: Match selector bits to case labels [OK]

Common Mistakes:

• Choosing default instead of matching case
• Mixing up input variables
• Ignoring binary selector format

4.

Identify the error in this Verilog case statement used for multiplexing:

always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
  endcase
end

medium

A. Missing default case for unmatched selector values

B. Incorrect use of always block sensitivity list

C. Wrong assignment operator used

D. Selector signal sel is not declared

Solution

1. Step 1: Check case completeness

   The case statement covers 2'b00, 2'b01, and 2'b10 but misses 2'b11.

2. Step 2: Importance of default case

   Without a default case, the output out may hold previous value or be undefined for unmatched selectors.

3. Final Answer:

   Missing default case for unmatched selector values -> Option A

4. Quick Check:

   Always include default in case [OK]

Hint: Always add default case in multiplexers [OK]

Common Mistakes:

• Forgetting default case
• Using wrong sensitivity list (@posedge instead of @(*) )
• Using '=' instead of '<=' in combinational logic

5.

You want to design a 4-to-1 multiplexer using a case statement in Verilog. Which of the following code snippets correctly implements this with inputs a, b, c, d, selector sel, and output out?

?

hard

A. always @(*) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
default: out = 1'b0;
endcase
end

B. always @(sel) begin
case(sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
default: out = d;
endcase
end

C. always @(*) begin
if(sel == 2'b00) out = a;
else if(sel == 2'b01) out = b;
else if(sel == 2'b10) out = c;
else out = d;
end

D. always @(*) begin
case(sel)
0: out = a;
1: out = b;
2: out = c;
3: out = d;
endcase
end

Solution

1. Step 1: Check sensitivity list

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end uses always @(*), which is correct for combinational logic multiplexers.

2. Step 2: Verify case labels and default

   always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end covers all 4 selector values (2'b00 to 2'b11) and includes a default case to avoid latches.

3. Step 3: Compare other options

   always @(sel) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; default: out = d; endcase end misses 2'b11 case explicitly and uses always @(sel) which is less recommended. always @(*) begin if(sel == 2'b00) out = a; else if(sel == 2'b01) out = b; else if(sel == 2'b10) out = c; else out = d; end uses if-else, not case. always @(*) begin case(sel) 0: out = a; 1: out = b; 2: out = c; 3: out = d; endcase end uses decimal labels without binary format and misses default.

4. Final Answer:

   Option A code snippet -> Option A

5. Quick Check:

   Complete case with default and always @(*) = always @(*) begin case(sel) 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 2'b11: out = d; default: out = 1'b0; endcase end [OK]

Hint: Use always @(*) and include default case [OK]

Common Mistakes:

• Omitting default case
• Using incomplete case labels
• Wrong sensitivity list
• Mixing if-else with case question