Case statement for multiplexing in Verilog - Mini Project: Build & Apply

Case Statement for Multiplexing in Verilog

📖 Scenario: You are designing a simple digital circuit that selects one of four 4-bit input signals based on a 2-bit selector signal. This is a common task in digital electronics called multiplexing.

🎯 Goal: Build a Verilog module that uses a case statement to select one of four 4-bit inputs and output it based on a 2-bit selector input.

📋 What You'll Learn

Create a Verilog module named mux4to1 with inputs and output as specified

Use a case statement inside an always block to implement the multiplexing logic

The module should have four 4-bit inputs named in0, in1, in2, in3

The module should have a 2-bit input named sel to select which input to output

The module should have a 4-bit output named out that reflects the selected input

💡 Why This Matters

🌍 Real World

Multiplexers are used in digital circuits to select one data source from many, saving hardware and routing signals efficiently.

💼 Career

Understanding multiplexers and case statements is essential for hardware design engineers and FPGA developers working with Verilog or VHDL.

1

Create the module and inputs/outputs

Write a Verilog module named mux4to1 with four 4-bit inputs called in0, in1, in2, in3, a 2-bit input called sel, and a 4-bit output called out. Declare out as reg.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

// Your code here

endmodule

Need a hint?

Remember to declare out as reg because it will be assigned inside an always block.

2

Add the always block with selector

Inside the mux4to1 module, add an always block that is sensitive to changes in sel, in0, in1, in2, and in3.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

always @ (sel or in0 or in1 or in2 or in3) begin
    // Your code here
end

endmodule

Need a hint?

The always block should react to changes in the selector and all inputs.

3

Implement the case statement for multiplexing

Inside the always block, write a case statement on sel that assigns out to in0 when sel is 0, in1 when sel is 1, in2 when sel is 2, and in3 when sel is 3. Include a default case that assigns out to 4'b0000.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

always @ (sel or in0 or in1 or in2 or in3) begin
    case (sel)
        // Your code here
    endcase
end

endmodule

Need a hint?

Use binary values for sel cases and assign out accordingly.

4

Test the module output

Write a testbench module named test_mux4to1 that instantiates mux4to1. Assign in0 = 4'b0001, in1 = 4'b0010, in2 = 4'b0100, in3 = 4'b1000. Change sel from 0 to 3 in steps, and use $display to print sel and out. Run the testbench to show the output.

Verilog

module mux4to1(
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] sel,
    output reg [3:0] out
);

always @ (sel or in0 or in1 or in2 or in3) begin
    case (sel)
        2'b00: out = in0;
        2'b01: out = in1;
        2'b10: out = in2;
        2'b11: out = in3;
        default: out = 4'b0000;
    endcase
end

endmodule

module test_mux4to1;
    reg [3:0] in0, in1, in2, in3;
    reg [1:0] sel;
    wire [3:0] out;

    mux4to1 uut(.in0(in0), .in1(in1), .in2(in2), .in3(in3), .sel(sel), .out(out));

    initial begin
        // Your code here
    end
endmodule

Need a hint?

Assign the inputs with the given values, change sel step by step, wait a little with #10, and print the values using $display.