When to use non-blocking (sequential) in Verilog - Step-by-Step Execution

Concept Flow - When to use non-blocking (sequential)

Start clock cycle

↓

Evaluate RHS expressions

↓

Schedule LHS updates (non-blocking)

↓

Complete all RHS evaluations

↓

Update all LHS variables simultaneously

↓

End clock cycle

Non-blocking assignments evaluate all right-hand sides first, then update left-hand sides together at the clock edge, ensuring sequential logic behaves correctly.

Execution Sample

Verilog

always @(posedge clk) begin
  a <= b;
  b <= c;
  c <= a;
end

This code updates variables a, b, c sequentially on clock edge using non-blocking assignments to avoid race conditions.

Execution Table

Step	a (old)	b (old)	c (old)	Evaluate RHS	Schedule LHS update	LHS after update
1 (clock edge)	0	1	2	a <= b (1), b <= c (2), c <= a (0)	Schedule a=1, b=2, c=0	a=1, b=2, c=0
2 (next clock)	1	2	0	a <= b (2), b <= c (0), c <= a (1)	Schedule a=2, b=0, c=1	a=2, b=0, c=1
3 (next clock)	2	0	1	a <= b (0), b <= c (1), c <= a (2)	Schedule a=0, b=1, c=2	a=0, b=1, c=2
4 (next clock)	0	1	2	a <= b (1), b <= c (2), c <= a (0)	Schedule a=1, b=2, c=0	a=1, b=2, c=0

💡 Execution continues each clock cycle, updating all variables simultaneously using non-blocking assignments.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4
a	0	1	2	0	1
b	1	2	0	1	2
c	2	0	1	2	0

Key Moments - 3 Insights

Why do all right-hand sides get evaluated before any left-hand side updates?

Because non-blocking assignments schedule updates to happen after all RHS expressions are evaluated, preventing race conditions as shown in execution_table step 1.

What would happen if blocking assignments were used instead?

Variables would update immediately, causing later RHS evaluations to use updated values, leading to incorrect sequential behavior unlike the simultaneous update in non-blocking shown here.

Why is it important that all LHS variables update simultaneously at the clock edge?

It models real hardware flip-flops updating together, ensuring predictable sequential logic behavior as demonstrated by the final LHS values in each clock cycle in execution_table.

Visual Quiz - 3 Questions

Look at the execution_table at step 2. What is the value of variable 'b' after the update?

A 0

B 2

C 1

D Undefined

💡 Hint

Check the 'LHS after update' column at step 2 for variable 'b'.

At which step does variable 'c' get the value 2?

A After step 1

B After step 2

C After step 3

D After step 4

💡 Hint

Look at the variable_tracker row for 'c' and find when it changes to 2.

If blocking assignments were used instead of non-blocking, how would the RHS evaluation change at step 1?

A All RHS use old values before any update

B RHS evaluations use updated values immediately after each assignment

C RHS evaluations are skipped

D RHS evaluations happen after LHS updates

💡 Hint

Recall the difference between blocking and non-blocking assignments in scheduling updates.

Concept Snapshot

Non-blocking assignments (<=) in sequential blocks:
- Evaluate all RHS first
- Schedule all LHS updates simultaneously at clock edge
- Prevent race conditions
- Model hardware flip-flop behavior
- Use in always @(posedge clk) blocks for sequential logic

Full Transcript

This visual execution shows how non-blocking assignments work in Verilog sequential logic. At each clock edge, all right-hand side expressions are evaluated first using old variable values. Then, all left-hand side variables are updated simultaneously. This prevents race conditions and models real hardware flip-flops updating together. The example code updates variables a, b, and c in a cycle. The execution table traces each clock cycle step by step, showing old values, RHS evaluations, scheduled updates, and final updated values. The variable tracker summarizes how each variable changes over time. Key moments clarify why RHS evaluation happens before LHS updates and why this is important. The quiz tests understanding of variable values at specific steps and the difference between blocking and non-blocking assignments. The snapshot summarizes the key rules for using non-blocking assignments in sequential Verilog code.