When to use non-blocking (sequential) in Verilog - Step-by-Step Execution

Concept Flow - When to use non-blocking (sequential)

Start clock cycle

↓

Evaluate RHS expressions

↓

Schedule LHS updates (non-blocking)

↓

Complete all RHS evaluations

↓

Update all LHS variables simultaneously

↓

End clock cycle

Non-blocking assignments evaluate all right-hand sides first, then update left-hand sides together at the clock edge, ensuring sequential logic behaves correctly.

Execution Sample

Verilog

always @(posedge clk) begin
  a <= b;
  b <= c;
  c <= a;
end

This code updates variables a, b, c sequentially on clock edge using non-blocking assignments to avoid race conditions.

Execution Table

Step	a (old)	b (old)	c (old)	Evaluate RHS	Schedule LHS update	LHS after update
1 (clock edge)	0	1	2	a <= b (1), b <= c (2), c <= a (0)	Schedule a=1, b=2, c=0	a=1, b=2, c=0
2 (next clock)	1	2	0	a <= b (2), b <= c (0), c <= a (1)	Schedule a=2, b=0, c=1	a=2, b=0, c=1
3 (next clock)	2	0	1	a <= b (0), b <= c (1), c <= a (2)	Schedule a=0, b=1, c=2	a=0, b=1, c=2
4 (next clock)	0	1	2	a <= b (1), b <= c (2), c <= a (0)	Schedule a=1, b=2, c=0	a=1, b=2, c=0

💡 Execution continues each clock cycle, updating all variables simultaneously using non-blocking assignments.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4
a	0	1	2	0	1
b	1	2	0	1	2
c	2	0	1	2	0

Key Moments - 3 Insights

Why do all right-hand sides get evaluated before any left-hand side updates?

Because non-blocking assignments schedule updates to happen after all RHS expressions are evaluated, preventing race conditions as shown in execution_table step 1.

What would happen if blocking assignments were used instead?

Variables would update immediately, causing later RHS evaluations to use updated values, leading to incorrect sequential behavior unlike the simultaneous update in non-blocking shown here.

Why is it important that all LHS variables update simultaneously at the clock edge?

It models real hardware flip-flops updating together, ensuring predictable sequential logic behavior as demonstrated by the final LHS values in each clock cycle in execution_table.

Visual Quiz - 3 Questions

Look at the execution_table at step 2. What is the value of variable 'b' after the update?

A 0

B 2

C 1

D Undefined

💡 Hint

Check the 'LHS after update' column at step 2 for variable 'b'.

At which step does variable 'c' get the value 2?

A After step 1

B After step 2

C After step 3

D After step 4

💡 Hint

Look at the variable_tracker row for 'c' and find when it changes to 2.

If blocking assignments were used instead of non-blocking, how would the RHS evaluation change at step 1?

A All RHS use old values before any update

B RHS evaluations use updated values immediately after each assignment

C RHS evaluations are skipped

D RHS evaluations happen after LHS updates

💡 Hint

Recall the difference between blocking and non-blocking assignments in scheduling updates.

Concept Snapshot

Non-blocking assignments (<=) in sequential blocks:
- Evaluate all RHS first
- Schedule all LHS updates simultaneously at clock edge
- Prevent race conditions
- Model hardware flip-flop behavior
- Use in always @(posedge clk) blocks for sequential logic

Full Transcript

This visual execution shows how non-blocking assignments work in Verilog sequential logic. At each clock edge, all right-hand side expressions are evaluated first using old variable values. Then, all left-hand side variables are updated simultaneously. This prevents race conditions and models real hardware flip-flops updating together. The example code updates variables a, b, and c in a cycle. The execution table traces each clock cycle step by step, showing old values, RHS evaluations, scheduled updates, and final updated values. The variable tracker summarizes how each variable changes over time. Key moments clarify why RHS evaluation happens before LHS updates and why this is important. The quiz tests understanding of variable values at specific steps and the difference between blocking and non-blocking assignments. The snapshot summarizes the key rules for using non-blocking assignments in sequential Verilog code.

Practice

1. When should you use non-blocking assignments (<=) in Verilog?

easy

A. To declare constants in your design

B. To model sequential logic that updates on clock edges

C. To model combinational logic with immediate updates

D. To assign values outside of always blocks

Solution

1. Step 1: Understand the purpose of non-blocking assignments

   Non-blocking assignments (<=) are used to model sequential logic, which updates values on clock edges, like flip-flops.

2. Step 2: Differentiate from other assignment types

   Blocking assignments (=) are used for combinational logic with immediate updates, not sequential logic.

3. Final Answer:

   To model sequential logic that updates on clock edges -> Option B

4. Quick Check:

   Non-blocking = sequential logic [OK]

Hint: Use non-blocking for clocked (sequential) logic only [OK]

Common Mistakes:

• Using non-blocking for combinational logic
• Confusing blocking and non-blocking assignments
• Assigning outside always blocks

2. Which of the following is the correct syntax for a non-blocking assignment inside an always block triggered on a clock edge?

easy

A. always @(posedge clk) begin a <= b; end

B. always @(posedge clk) begin a = b; end

C. always @(clk) begin a <= b; end

D. always @(posedge clk) a = b;

Solution

1. Step 1: Identify the correct event control

   The always block should trigger on the positive edge of the clock: posedge clk.

2. Step 2: Use non-blocking assignment inside the block

   Non-blocking assignment uses <= to update signals sequentially.

3. Final Answer:

   always @(posedge clk) begin a <= b; end -> Option A

4. Quick Check:

   Non-blocking inside posedge always block = correct syntax [OK]

Hint: Use '<= ' inside 'always @(posedge clk)' for sequential logic [OK]

Common Mistakes:

• Using blocking '=' instead of '<=' in sequential blocks
• Triggering always block on wrong event
• Missing begin-end for multiple statements

3. What is the output of this Verilog code snippet after one positive clock edge?

reg a, b;
always @(posedge clk) begin
  a <= b;
  b <= 1'b1;
end

Assuming initial values a=0 and b=0.

medium

A. a=0, b=1

B. a=1, b=1

C. a=0, b=0

D. a=1, b=0

Solution

1. Step 1: Understand non-blocking update behavior

   Non-blocking assignments update all variables simultaneously after the always block finishes.

2. Step 2: Trace values before and after clock edge

   Before clock edge: a=0, b=0.
   At clock edge: a gets old b (0), b gets 1.
   After update: a=0, b=1.

3. Final Answer:

   a=0, b=1 -> Option A

4. Quick Check:

   Non-blocking updates use old values simultaneously [OK]

Hint: Non-blocking uses old values simultaneously on clock edge [OK]

Common Mistakes:

• Thinking 'a' updates immediately with new 'b'
• Confusing blocking and non-blocking timing
• Ignoring initial values

4. Identify the error in this Verilog code snippet:

always @(posedge clk) begin
  a = b;
  b = 1'b1;
end

where a and b are registers updated on clock edge.

medium

A. Missing sensitivity list for combinational logic

B. Using non-blocking assignments outside always block

C. Incorrect data types for registers

D. Using blocking assignments instead of non-blocking in sequential logic

Solution

1. Step 1: Check assignment type in clocked always block

   Sequential logic triggered on clock edges should use non-blocking assignments (<=), not blocking (=).

2. Step 2: Understand consequences of blocking in sequential logic

   Blocking assignments cause race conditions and incorrect simulation of flip-flops.

3. Final Answer:

   Using blocking assignments instead of non-blocking in sequential logic -> Option D

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use '<=' in clocked always blocks to avoid race conditions [OK]

Common Mistakes:

• Using '=' in clocked always blocks
• Ignoring race condition risks
• Confusing sensitivity lists

5. You want to design a 2-bit register that updates both bits simultaneously on the rising edge of clk. Which code snippet correctly uses non-blocking assignments to avoid race conditions?

A) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit0;
end

B) always @(posedge clk) begin
  bit0 = bit1;
  bit1 = bit0;
end

C) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit1;
end

D) always @(posedge clk) begin
  bit0 = bit0;
  bit1 = bit1;
end

hard

A. Assigns bit1 to both bits, losing original bit0

B. Uses blocking assignments causing race conditions

C. Swaps bits correctly using non-blocking assignments

D. No change in bits, blocking assignments used

Solution

1. Step 1: Analyze non-blocking assignments in Swaps bits correctly using non-blocking assignments

   Swaps bits correctly using non-blocking assignments uses non-blocking assignments to swap bit0 and bit1 simultaneously, avoiding race conditions.

2. Step 2: Compare with other options

   Uses blocking assignments causing race conditions uses blocking assignments causing race conditions.
   Assigns bit1 to both bits, losing original bit0 overwrites bit0 and bit1 incorrectly.
   No change in bits, blocking assignments used does not change bits and uses blocking assignments.

3. Final Answer:

   Swaps bits correctly using non-blocking assignments -> Option C

4. Quick Check:

   Non-blocking swaps bits simultaneously [OK]

Hint: Use non-blocking to swap registers simultaneously on clock edge [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Overwriting values before reading them
• Not updating both bits simultaneously