When to use non-blocking (sequential) in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a non-blocking assignment in Verilog?

A non-blocking assignment uses the '<=' operator and schedules the assignment to happen at the end of the current time step, allowing all right-hand side expressions to be evaluated before updating the left-hand side.

beginner

Why should non-blocking assignments be used in sequential logic?

Non-blocking assignments prevent race conditions by updating all registers simultaneously at the end of the clock cycle, which models real hardware flip-flop behavior.

intermediate

When should blocking assignments be avoided in sequential always blocks?

Blocking assignments should be avoided in sequential always blocks because they update variables immediately, which can cause unintended ordering and simulation mismatches with hardware.

intermediate

How does non-blocking assignment help in modeling flip-flops?

Non-blocking assignments update all outputs simultaneously after evaluating inputs, mimicking how flip-flops capture data on clock edges in real hardware.

advanced

What is a common mistake when mixing blocking and non-blocking assignments in sequential logic?

Mixing blocking and non-blocking assignments in the same always block can cause simulation mismatches and unpredictable behavior because of different update timings.

Which operator is used for non-blocking assignments in Verilog?

A !=

B =

C ==

D <=

The '<=' operator is used for non-blocking assignments, which schedule updates at the end of the time step.

Why use non-blocking assignments in sequential always blocks?

A To update variables immediately in order

B To update all registers simultaneously after evaluation

C To save memory

D To make code run faster

Non-blocking assignments update all registers simultaneously, matching hardware flip-flop behavior.

What happens if blocking assignments are used in sequential logic?

A Variables update at the end of the time step

B Code will not compile

C Variables update immediately, possibly causing race conditions

D Simulation runs faster

Blocking assignments update immediately, which can cause race conditions in sequential logic.

Which type of assignment models flip-flop behavior best?

A Non-blocking assignment

B Blocking assignment

C Continuous assignment

D Conditional assignment

Non-blocking assignments model flip-flops by updating outputs simultaneously after evaluation.

What is a risk of mixing blocking and non-blocking assignments in the same always block?

A Unpredictable simulation behavior

B Faster simulation

C Cleaner code

D No effect

Mixing assignment types can cause unpredictable simulation results due to different update timings.

Explain why non-blocking assignments are preferred in sequential logic blocks in Verilog.

Think about how hardware flip-flops update on clock edges.

Describe the problems that can arise if blocking assignments are used in sequential always blocks.

Consider timing differences between blocking and non-blocking assignments.

Practice

1. When should you use non-blocking assignments (<=) in Verilog?

easy

A. To declare constants in your design

B. To model sequential logic that updates on clock edges

C. To model combinational logic with immediate updates

D. To assign values outside of always blocks

Solution

1. Step 1: Understand the purpose of non-blocking assignments

   Non-blocking assignments (<=) are used to model sequential logic, which updates values on clock edges, like flip-flops.

2. Step 2: Differentiate from other assignment types

   Blocking assignments (=) are used for combinational logic with immediate updates, not sequential logic.

3. Final Answer:

   To model sequential logic that updates on clock edges -> Option B

4. Quick Check:

   Non-blocking = sequential logic [OK]

Hint: Use non-blocking for clocked (sequential) logic only [OK]

Common Mistakes:

• Using non-blocking for combinational logic
• Confusing blocking and non-blocking assignments
• Assigning outside always blocks

2. Which of the following is the correct syntax for a non-blocking assignment inside an always block triggered on a clock edge?

easy

A. always @(posedge clk) begin a <= b; end

B. always @(posedge clk) begin a = b; end

C. always @(clk) begin a <= b; end

D. always @(posedge clk) a = b;

Solution

1. Step 1: Identify the correct event control

   The always block should trigger on the positive edge of the clock: posedge clk.

2. Step 2: Use non-blocking assignment inside the block

   Non-blocking assignment uses <= to update signals sequentially.

3. Final Answer:

   always @(posedge clk) begin a <= b; end -> Option A

4. Quick Check:

   Non-blocking inside posedge always block = correct syntax [OK]

Hint: Use '<= ' inside 'always @(posedge clk)' for sequential logic [OK]

Common Mistakes:

• Using blocking '=' instead of '<=' in sequential blocks
• Triggering always block on wrong event
• Missing begin-end for multiple statements

3. What is the output of this Verilog code snippet after one positive clock edge?

reg a, b;
always @(posedge clk) begin
  a <= b;
  b <= 1'b1;
end

Assuming initial values a=0 and b=0.

medium

A. a=0, b=1

B. a=1, b=1

C. a=0, b=0

D. a=1, b=0

Solution

1. Step 1: Understand non-blocking update behavior

   Non-blocking assignments update all variables simultaneously after the always block finishes.

2. Step 2: Trace values before and after clock edge

   Before clock edge: a=0, b=0.
   At clock edge: a gets old b (0), b gets 1.
   After update: a=0, b=1.

3. Final Answer:

   a=0, b=1 -> Option A

4. Quick Check:

   Non-blocking updates use old values simultaneously [OK]

Hint: Non-blocking uses old values simultaneously on clock edge [OK]

Common Mistakes:

• Thinking 'a' updates immediately with new 'b'
• Confusing blocking and non-blocking timing
• Ignoring initial values

4. Identify the error in this Verilog code snippet:

always @(posedge clk) begin
  a = b;
  b = 1'b1;
end

where a and b are registers updated on clock edge.

medium

A. Missing sensitivity list for combinational logic

B. Using non-blocking assignments outside always block

C. Incorrect data types for registers

D. Using blocking assignments instead of non-blocking in sequential logic

Solution

1. Step 1: Check assignment type in clocked always block

   Sequential logic triggered on clock edges should use non-blocking assignments (<=), not blocking (=).

2. Step 2: Understand consequences of blocking in sequential logic

   Blocking assignments cause race conditions and incorrect simulation of flip-flops.

3. Final Answer:

   Using blocking assignments instead of non-blocking in sequential logic -> Option D

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use '<=' in clocked always blocks to avoid race conditions [OK]

Common Mistakes:

• Using '=' in clocked always blocks
• Ignoring race condition risks
• Confusing sensitivity lists

5. You want to design a 2-bit register that updates both bits simultaneously on the rising edge of clk. Which code snippet correctly uses non-blocking assignments to avoid race conditions?

A) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit0;
end

B) always @(posedge clk) begin
  bit0 = bit1;
  bit1 = bit0;
end

C) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit1;
end

D) always @(posedge clk) begin
  bit0 = bit0;
  bit1 = bit1;
end

hard

A. Assigns bit1 to both bits, losing original bit0

B. Uses blocking assignments causing race conditions

C. Swaps bits correctly using non-blocking assignments

D. No change in bits, blocking assignments used

Solution

1. Step 1: Analyze non-blocking assignments in Swaps bits correctly using non-blocking assignments

   Swaps bits correctly using non-blocking assignments uses non-blocking assignments to swap bit0 and bit1 simultaneously, avoiding race conditions.

2. Step 2: Compare with other options

   Uses blocking assignments causing race conditions uses blocking assignments causing race conditions.
   Assigns bit1 to both bits, losing original bit0 overwrites bit0 and bit1 incorrectly.
   No change in bits, blocking assignments used does not change bits and uses blocking assignments.

3. Final Answer:

   Swaps bits correctly using non-blocking assignments -> Option C

4. Quick Check:

   Non-blocking swaps bits simultaneously [OK]

Hint: Use non-blocking to swap registers simultaneously on clock edge [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Overwriting values before reading them
• Not updating both bits simultaneously