When to use non-blocking (sequential) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of non-blocking assignments in sequential logic

What is the output of the following Verilog code snippet after one clock cycle?

reg [3:0] a, b;
always @(posedge clk) begin
  a <= b;
  b <= a + 1;
end

Verilog

reg [3:0] a = 0, b = 0;
always @(posedge clk) begin
  a <= b;
  b <= a + 1;
end
// After one positive clock edge, what are the values of a and b?

A a = 1, b = 1

B a = 0, b = 1

C a = 0, b = 0

D a = 1, b = 0

💡 Hint

Remember that non-blocking assignments update all variables simultaneously after the always block finishes.

Non-blocking assignments (<=) schedule updates to happen at the end of the time step. So, 'a' gets the old value of 'b' (which is 0), and 'b' gets the old value of 'a' plus 1 (0 + 1 = 1). Thus, after the clock edge, a=0 and b=1.

🧠 Conceptual

intermediate

Why use non-blocking assignments in sequential always blocks?

Which reason best explains why non-blocking assignments (<=) are preferred in sequential always blocks triggered by clock edges?

A They automatically infer combinational logic without needing sensitivity lists.

B They execute assignments immediately, making simulation faster.

C They are simpler to write and require less code than blocking assignments.

D They allow all right-hand side expressions to be evaluated before any left-hand side variables are updated, preventing race conditions.

💡 Hint

Think about how multiple assignments inside a clocked block should behave simultaneously.

Non-blocking assignments schedule all updates to happen simultaneously after evaluating the right-hand sides. This prevents race conditions and ensures correct sequential logic behavior.

🔧 Debug

advanced

Identify the problem with blocking assignments in sequential logic

Consider this Verilog code inside a clocked always block:

always @(posedge clk) begin
  a = b;
  b = a + 1;
end

What problem will this cause?

A It causes a race condition because 'a' is updated immediately, affecting the next assignment to 'b'.

B It will synthesize correctly with no issues.

C It causes a syntax error because blocking assignments are not allowed in always blocks.

D It will cause 'b' to never update.

💡 Hint

Think about how blocking assignments execute in order inside an always block.

Blocking assignments (=) update variables immediately. So 'a = b;' updates 'a' before 'b = a + 1;' executes, causing 'b' to use the new 'a' value, not the old one. This creates unintended behavior and race conditions.

📝 Syntax

advanced

Which code correctly uses non-blocking assignments in sequential logic?

Which of the following always blocks correctly uses non-blocking assignments for sequential logic?

A

always @(posedge clk) begin
  x <= y;
  y <= x + 1;
end

B

always @(posedge clk) begin
  x = y;
  y = x + 1;
end

C

always @(*) begin
  x <= y;
  y <= x + 1;
end

D

always @(*) begin
  x = y;
  y = x + 1;
end

💡 Hint

Non-blocking assignments are used in clocked always blocks, not combinational ones.

Option A uses non-blocking assignments (<=) inside a clocked always block (posedge clk), which is the correct style for sequential logic. Options C and D use combinational always blocks (@(*)). Option A uses blocking assignments (=) in a clocked block, which is discouraged.

🚀 Application

expert

Predict the final values after multiple clock cycles with non-blocking assignments

Given the following Verilog code, what are the values of a and b after 3 positive clock edges?

reg [3:0] a = 0, b = 0;
always @(posedge clk) begin
  a <= b;
  b <= a + 1;
end

A After 3 cycles: a = 3, b = 4

B After 3 cycles: a = 3, b = 3

C After 3 cycles: a = 2, b = 3

D After 3 cycles: a = 1, b = 2

💡 Hint

Trace the values step-by-step, remembering non-blocking assignments update simultaneously after each clock.

Cycle 1: a=0, b=1
Cycle 2: a=1, b=2
Cycle 3: a=2, b=3
Each cycle, 'a' takes previous 'b', and 'b' takes previous 'a' + 1.

Practice

1. When should you use non-blocking assignments (<=) in Verilog?

easy

A. To declare constants in your design

B. To model sequential logic that updates on clock edges

C. To model combinational logic with immediate updates

D. To assign values outside of always blocks

Solution

1. Step 1: Understand the purpose of non-blocking assignments

   Non-blocking assignments (<=) are used to model sequential logic, which updates values on clock edges, like flip-flops.

2. Step 2: Differentiate from other assignment types

   Blocking assignments (=) are used for combinational logic with immediate updates, not sequential logic.

3. Final Answer:

   To model sequential logic that updates on clock edges -> Option B

4. Quick Check:

   Non-blocking = sequential logic [OK]

Hint: Use non-blocking for clocked (sequential) logic only [OK]

Common Mistakes:

• Using non-blocking for combinational logic
• Confusing blocking and non-blocking assignments
• Assigning outside always blocks

2. Which of the following is the correct syntax for a non-blocking assignment inside an always block triggered on a clock edge?

easy

A. always @(posedge clk) begin a <= b; end

B. always @(posedge clk) begin a = b; end

C. always @(clk) begin a <= b; end

D. always @(posedge clk) a = b;

Solution

1. Step 1: Identify the correct event control

   The always block should trigger on the positive edge of the clock: posedge clk.

2. Step 2: Use non-blocking assignment inside the block

   Non-blocking assignment uses <= to update signals sequentially.

3. Final Answer:

   always @(posedge clk) begin a <= b; end -> Option A

4. Quick Check:

   Non-blocking inside posedge always block = correct syntax [OK]

Hint: Use '<= ' inside 'always @(posedge clk)' for sequential logic [OK]

Common Mistakes:

• Using blocking '=' instead of '<=' in sequential blocks
• Triggering always block on wrong event
• Missing begin-end for multiple statements

3. What is the output of this Verilog code snippet after one positive clock edge?

reg a, b;
always @(posedge clk) begin
  a <= b;
  b <= 1'b1;
end

Assuming initial values a=0 and b=0.

medium

A. a=0, b=1

B. a=1, b=1

C. a=0, b=0

D. a=1, b=0

Solution

1. Step 1: Understand non-blocking update behavior

   Non-blocking assignments update all variables simultaneously after the always block finishes.

2. Step 2: Trace values before and after clock edge

   Before clock edge: a=0, b=0.
   At clock edge: a gets old b (0), b gets 1.
   After update: a=0, b=1.

3. Final Answer:

   a=0, b=1 -> Option A

4. Quick Check:

   Non-blocking updates use old values simultaneously [OK]

Hint: Non-blocking uses old values simultaneously on clock edge [OK]

Common Mistakes:

• Thinking 'a' updates immediately with new 'b'
• Confusing blocking and non-blocking timing
• Ignoring initial values

4. Identify the error in this Verilog code snippet:

always @(posedge clk) begin
  a = b;
  b = 1'b1;
end

where a and b are registers updated on clock edge.

medium

A. Missing sensitivity list for combinational logic

B. Using non-blocking assignments outside always block

C. Incorrect data types for registers

D. Using blocking assignments instead of non-blocking in sequential logic

Solution

1. Step 1: Check assignment type in clocked always block

   Sequential logic triggered on clock edges should use non-blocking assignments (<=), not blocking (=).

2. Step 2: Understand consequences of blocking in sequential logic

   Blocking assignments cause race conditions and incorrect simulation of flip-flops.

3. Final Answer:

   Using blocking assignments instead of non-blocking in sequential logic -> Option D

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use '<=' in clocked always blocks to avoid race conditions [OK]

Common Mistakes:

• Using '=' in clocked always blocks
• Ignoring race condition risks
• Confusing sensitivity lists

5. You want to design a 2-bit register that updates both bits simultaneously on the rising edge of clk. Which code snippet correctly uses non-blocking assignments to avoid race conditions?

A) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit0;
end

B) always @(posedge clk) begin
  bit0 = bit1;
  bit1 = bit0;
end

C) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit1;
end

D) always @(posedge clk) begin
  bit0 = bit0;
  bit1 = bit1;
end

hard

A. Assigns bit1 to both bits, losing original bit0

B. Uses blocking assignments causing race conditions

C. Swaps bits correctly using non-blocking assignments

D. No change in bits, blocking assignments used

Solution

1. Step 1: Analyze non-blocking assignments in Swaps bits correctly using non-blocking assignments

   Swaps bits correctly using non-blocking assignments uses non-blocking assignments to swap bit0 and bit1 simultaneously, avoiding race conditions.

2. Step 2: Compare with other options

   Uses blocking assignments causing race conditions uses blocking assignments causing race conditions.
   Assigns bit1 to both bits, losing original bit0 overwrites bit0 and bit1 incorrectly.
   No change in bits, blocking assignments used does not change bits and uses blocking assignments.

3. Final Answer:

   Swaps bits correctly using non-blocking assignments -> Option C

4. Quick Check:

   Non-blocking swaps bits simultaneously [OK]

Hint: Use non-blocking to swap registers simultaneously on clock edge [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Overwriting values before reading them
• Not updating both bits simultaneously