When to use non-blocking (sequential) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of non-blocking assignments in sequential logic

What is the output of the following Verilog code snippet after one clock cycle?

reg [3:0] a, b;
always @(posedge clk) begin
  a <= b;
  b <= a + 1;
end

Verilog

reg [3:0] a = 0, b = 0;
always @(posedge clk) begin
  a <= b;
  b <= a + 1;
end
// After one positive clock edge, what are the values of a and b?

A a = 1, b = 1

B a = 0, b = 1

C a = 0, b = 0

D a = 1, b = 0

💡 Hint

Remember that non-blocking assignments update all variables simultaneously after the always block finishes.

Non-blocking assignments (<=) schedule updates to happen at the end of the time step. So, 'a' gets the old value of 'b' (which is 0), and 'b' gets the old value of 'a' plus 1 (0 + 1 = 1). Thus, after the clock edge, a=0 and b=1.

🧠 Conceptual

intermediate

Why use non-blocking assignments in sequential always blocks?

Which reason best explains why non-blocking assignments (<=) are preferred in sequential always blocks triggered by clock edges?

A They automatically infer combinational logic without needing sensitivity lists.

B They execute assignments immediately, making simulation faster.

C They are simpler to write and require less code than blocking assignments.

D They allow all right-hand side expressions to be evaluated before any left-hand side variables are updated, preventing race conditions.

💡 Hint

Think about how multiple assignments inside a clocked block should behave simultaneously.

Non-blocking assignments schedule all updates to happen simultaneously after evaluating the right-hand sides. This prevents race conditions and ensures correct sequential logic behavior.

🔧 Debug

advanced

Identify the problem with blocking assignments in sequential logic

Consider this Verilog code inside a clocked always block:

always @(posedge clk) begin
  a = b;
  b = a + 1;
end

What problem will this cause?

A It causes a race condition because 'a' is updated immediately, affecting the next assignment to 'b'.

B It will synthesize correctly with no issues.

C It causes a syntax error because blocking assignments are not allowed in always blocks.

D It will cause 'b' to never update.

💡 Hint

Think about how blocking assignments execute in order inside an always block.

Blocking assignments (=) update variables immediately. So 'a = b;' updates 'a' before 'b = a + 1;' executes, causing 'b' to use the new 'a' value, not the old one. This creates unintended behavior and race conditions.

📝 Syntax

advanced

Which code correctly uses non-blocking assignments in sequential logic?

Which of the following always blocks correctly uses non-blocking assignments for sequential logic?

A

always @(posedge clk) begin
  x <= y;
  y <= x + 1;
end

B

always @(posedge clk) begin
  x = y;
  y = x + 1;
end

C

always @(*) begin
  x <= y;
  y <= x + 1;
end

D

always @(*) begin
  x = y;
  y = x + 1;
end

💡 Hint

Non-blocking assignments are used in clocked always blocks, not combinational ones.

Option A uses non-blocking assignments (<=) inside a clocked always block (posedge clk), which is the correct style for sequential logic. Options C and D use combinational always blocks (@(*)). Option A uses blocking assignments (=) in a clocked block, which is discouraged.

🚀 Application

expert

Predict the final values after multiple clock cycles with non-blocking assignments

Given the following Verilog code, what are the values of a and b after 3 positive clock edges?

reg [3:0] a = 0, b = 0;
always @(posedge clk) begin
  a <= b;
  b <= a + 1;
end

A After 3 cycles: a = 3, b = 4

B After 3 cycles: a = 3, b = 3

C After 3 cycles: a = 2, b = 3

D After 3 cycles: a = 1, b = 2

💡 Hint

Trace the values step-by-step, remembering non-blocking assignments update simultaneously after each clock.

Cycle 1: a=0, b=1
Cycle 2: a=1, b=2
Cycle 3: a=2, b=3
Each cycle, 'a' takes previous 'b', and 'b' takes previous 'a' + 1.