When to use non-blocking (sequential) in Verilog - Mini Project: Build & Apply

When to use non-blocking (sequential) in Verilog

📖 Scenario: You are designing a simple digital circuit that counts the number of clock cycles. You want to update the count correctly on each clock edge without errors caused by simultaneous updates.

🎯 Goal: Build a Verilog module that uses non-blocking assignments to update a counter sequentially on the clock's rising edge.

📋 What You'll Learn

Create a 4-bit register called count initialized to 0

Create a clock input called clk

Use a non-blocking assignment inside an always @(posedge clk) block to increment count

Print the new value of count after each clock cycle

💡 Why This Matters

🌍 Real World

Counters are used in many digital circuits like timers, frequency dividers, and state machines. Using non-blocking assignments ensures the counter updates correctly on clock edges.

💼 Career

Understanding when to use non-blocking assignments is essential for hardware design engineers working with synchronous digital circuits and FPGA or ASIC development.

1

DATA SETUP: Create a 4-bit register called count initialized to 0

Write a Verilog line to declare a 4-bit register named count and initialize it to 0.

Verilog

reg [3:0] count = 0;  // Your code here

Need a hint?

Use reg [3:0] count = 0; to declare a 4-bit register initialized to zero.

2

CONFIGURATION: Declare an input clock signal called clk

Add a line to declare an input signal named clk to represent the clock.

Verilog

input clk;  // Your code here
reg [3:0] count = 0;

Need a hint?

Use input clk; to declare the clock input.

3

CORE LOGIC: Use a non-blocking assignment inside an always block triggered on the rising edge of clk to increment count

Write an always @(posedge clk) block that increments count by 1 using a non-blocking assignment <=.

Verilog

input clk;
reg [3:0] count = 0;

always @(posedge clk) begin
    // Your code here
end

Need a hint?

Use always @(posedge clk) and inside it write count <= count + 1; to update count sequentially.

4

OUTPUT: Display the value of count after each clock cycle

Add a line to print the new value of count inside the always block after the assignment using $display.

Verilog

input clk;
reg [3:0] count = 0;

always @(posedge clk) begin
    count <= count + 1;
    // Your code here
end

Need a hint?

Use $display("Count value: %d", count + 1); to print the new count value.