When to use non-blocking (sequential) in Verilog - Mini Project: Build & Apply

When to use non-blocking (sequential) in Verilog

📖 Scenario: You are designing a simple digital circuit that counts the number of clock cycles. You want to update the count correctly on each clock edge without errors caused by simultaneous updates.

🎯 Goal: Build a Verilog module that uses non-blocking assignments to update a counter sequentially on the clock's rising edge.

📋 What You'll Learn

Create a 4-bit register called count initialized to 0

Create a clock input called clk

Use a non-blocking assignment inside an always @(posedge clk) block to increment count

Print the new value of count after each clock cycle

💡 Why This Matters

🌍 Real World

Counters are used in many digital circuits like timers, frequency dividers, and state machines. Using non-blocking assignments ensures the counter updates correctly on clock edges.

💼 Career

Understanding when to use non-blocking assignments is essential for hardware design engineers working with synchronous digital circuits and FPGA or ASIC development.

1

DATA SETUP: Create a 4-bit register called count initialized to 0

Write a Verilog line to declare a 4-bit register named count and initialize it to 0.

Verilog

reg [3:0] count = 0;  // Your code here

Hint

Use reg [3:0] count = 0; to declare a 4-bit register initialized to zero.

2

CONFIGURATION: Declare an input clock signal called clk

Add a line to declare an input signal named clk to represent the clock.

Verilog

input clk;  // Your code here
reg [3:0] count = 0;

Hint

Use input clk; to declare the clock input.

3

CORE LOGIC: Use a non-blocking assignment inside an always block triggered on the rising edge of clk to increment count

Write an always @(posedge clk) block that increments count by 1 using a non-blocking assignment <=.

Verilog

input clk;
reg [3:0] count = 0;

always @(posedge clk) begin
    // Your code here
end

Hint

Use always @(posedge clk) and inside it write count <= count + 1; to update count sequentially.

4

OUTPUT: Display the value of count after each clock cycle

Add a line to print the new value of count inside the always block after the assignment using $display.

Verilog

input clk;
reg [3:0] count = 0;

always @(posedge clk) begin
    count <= count + 1;
    // Your code here
end

Hint

Use $display("Count value: %d", count + 1); to print the new count value.

Practice

1. When should you use non-blocking assignments (<=) in Verilog?

easy

A. To declare constants in your design

B. To model sequential logic that updates on clock edges

C. To model combinational logic with immediate updates

D. To assign values outside of always blocks

Solution

1. Step 1: Understand the purpose of non-blocking assignments

   Non-blocking assignments (<=) are used to model sequential logic, which updates values on clock edges, like flip-flops.

2. Step 2: Differentiate from other assignment types

   Blocking assignments (=) are used for combinational logic with immediate updates, not sequential logic.

3. Final Answer:

   To model sequential logic that updates on clock edges -> Option B

4. Quick Check:

   Non-blocking = sequential logic [OK]

Hint: Use non-blocking for clocked (sequential) logic only [OK]

Common Mistakes:

• Using non-blocking for combinational logic
• Confusing blocking and non-blocking assignments
• Assigning outside always blocks

2. Which of the following is the correct syntax for a non-blocking assignment inside an always block triggered on a clock edge?

easy

A. always @(posedge clk) begin a <= b; end

B. always @(posedge clk) begin a = b; end

C. always @(clk) begin a <= b; end

D. always @(posedge clk) a = b;

Solution

1. Step 1: Identify the correct event control

   The always block should trigger on the positive edge of the clock: posedge clk.

2. Step 2: Use non-blocking assignment inside the block

   Non-blocking assignment uses <= to update signals sequentially.

3. Final Answer:

   always @(posedge clk) begin a <= b; end -> Option A

4. Quick Check:

   Non-blocking inside posedge always block = correct syntax [OK]

Hint: Use '<= ' inside 'always @(posedge clk)' for sequential logic [OK]

Common Mistakes:

• Using blocking '=' instead of '<=' in sequential blocks
• Triggering always block on wrong event
• Missing begin-end for multiple statements

3. What is the output of this Verilog code snippet after one positive clock edge?

reg a, b;
always @(posedge clk) begin
  a <= b;
  b <= 1'b1;
end

Assuming initial values a=0 and b=0.

medium

A. a=0, b=1

B. a=1, b=1

C. a=0, b=0

D. a=1, b=0

Solution

1. Step 1: Understand non-blocking update behavior

   Non-blocking assignments update all variables simultaneously after the always block finishes.

2. Step 2: Trace values before and after clock edge

   Before clock edge: a=0, b=0.
   At clock edge: a gets old b (0), b gets 1.
   After update: a=0, b=1.

3. Final Answer:

   a=0, b=1 -> Option A

4. Quick Check:

   Non-blocking updates use old values simultaneously [OK]

Hint: Non-blocking uses old values simultaneously on clock edge [OK]

Common Mistakes:

• Thinking 'a' updates immediately with new 'b'
• Confusing blocking and non-blocking timing
• Ignoring initial values

4. Identify the error in this Verilog code snippet:

always @(posedge clk) begin
  a = b;
  b = 1'b1;
end

where a and b are registers updated on clock edge.

medium

A. Missing sensitivity list for combinational logic

B. Using non-blocking assignments outside always block

C. Incorrect data types for registers

D. Using blocking assignments instead of non-blocking in sequential logic

Solution

1. Step 1: Check assignment type in clocked always block

   Sequential logic triggered on clock edges should use non-blocking assignments (<=), not blocking (=).

2. Step 2: Understand consequences of blocking in sequential logic

   Blocking assignments cause race conditions and incorrect simulation of flip-flops.

3. Final Answer:

   Using blocking assignments instead of non-blocking in sequential logic -> Option D

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use '<=' in clocked always blocks to avoid race conditions [OK]

Common Mistakes:

• Using '=' in clocked always blocks
• Ignoring race condition risks
• Confusing sensitivity lists

5. You want to design a 2-bit register that updates both bits simultaneously on the rising edge of clk. Which code snippet correctly uses non-blocking assignments to avoid race conditions?

A) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit0;
end

B) always @(posedge clk) begin
  bit0 = bit1;
  bit1 = bit0;
end

C) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit1;
end

D) always @(posedge clk) begin
  bit0 = bit0;
  bit1 = bit1;
end

hard

A. Assigns bit1 to both bits, losing original bit0

B. Uses blocking assignments causing race conditions

C. Swaps bits correctly using non-blocking assignments

D. No change in bits, blocking assignments used

Solution

1. Step 1: Analyze non-blocking assignments in Swaps bits correctly using non-blocking assignments

   Swaps bits correctly using non-blocking assignments uses non-blocking assignments to swap bit0 and bit1 simultaneously, avoiding race conditions.

2. Step 2: Compare with other options

   Uses blocking assignments causing race conditions uses blocking assignments causing race conditions.
   Assigns bit1 to both bits, losing original bit0 overwrites bit0 and bit1 incorrectly.
   No change in bits, blocking assignments used does not change bits and uses blocking assignments.

3. Final Answer:

   Swaps bits correctly using non-blocking assignments -> Option C

4. Quick Check:

   Non-blocking swaps bits simultaneously [OK]

Hint: Use non-blocking to swap registers simultaneously on clock edge [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Overwriting values before reading them
• Not updating both bits simultaneously