Up-down counter with direction control in Verilog - Step-by-Step Execution

Concept Flow - Up-down counter with direction control

Start

↓

Check direction

↓

Up

↓

Increment

↓

Update counter

↓

Output

↓

End

The counter checks the direction input; if up, it increments the count; if down, it decrements the count, then updates the output.

Execution Sample

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 0;
  else if (dir)
    count <= count + 1;
  else
    count <= count - 1;
end

This code resets the counter or increments/decrements it based on the direction signal at each clock pulse.

Execution Table

Step	reset	dir	count before	Condition	Action	count after	Output
1	1	X	X	reset=1	Reset count to 0	0	0
2	0	1	0	dir=1	Increment count	1	1
3	0	1	1	dir=1	Increment count	2	2
4	0	0	2	dir=0	Decrement count	1	1
5	0	0	1	dir=0	Decrement count	0	0
6	0	1	0	dir=1	Increment count	1	1
7	1	X	1	reset=1	Reset count to 0	0	0

💡 Simulation ends after reset is asserted again at step 7.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7
count	X	0	1	2	1	0	1	0
reset	X	1	0	0	0	0	0	1
dir	X	X	1	1	0	0	1	X

Key Moments - 3 Insights

Why does the count reset to 0 even if dir is 1 or 0?

Because reset has the highest priority in the if-else chain (see step 1 and 7 in execution_table), it resets count regardless of dir.

What happens if dir changes while reset is 0?

The counter increments if dir=1 or decrements if dir=0, as shown in steps 2-6 in execution_table.

Why is count before 'X' at step 1?

At the start, count is undefined (X), but reset sets it to 0 immediately (step 1).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of count after step 4?

A 2

B 0

C 1

D 3

💡 Hint

Check the 'count after' column at step 4 in execution_table.

At which step does the reset signal cause the count to become 0 again?

A Step 7

B Step 2

C Step 5

D Step 4

💡 Hint

Look for rows where reset=1 and count after=0 in execution_table.

If dir was always 0 and reset never asserted after start, what would happen to count?

A It would keep incrementing

B It would keep decrementing

C It would stay at 0

D It would reset repeatedly

💡 Hint

Refer to variable_tracker and execution_table steps where dir=0 and reset=0.

Concept Snapshot

Up-down counter with direction control in Verilog:
- Use always block triggered by posedge clk or reset
- If reset=1, count=0 (highest priority)
- Else if dir=1, count increments
- Else count decrements
- Output count value each clock cycle

Full Transcript

This visual execution trace shows an up-down counter in Verilog controlled by a direction signal and reset. The counter resets to zero when reset is high. When reset is low, if direction is high, the counter increments by one each clock cycle; if direction is low, it decrements by one. The execution table tracks each step with signals and count values. Variable tracker shows how count, reset, and dir change over time. Key moments clarify priority of reset and behavior of direction. The quiz tests understanding of count values at specific steps and effects of signals.

Practice

1. What does the direction signal control in an up-down counter in Verilog?

easy

A. The reset state of the counter

B. The speed of the clock signal

C. Whether the counter counts up or down

D. The width of the counter output

Solution

1. Step 1: Understand the role of the direction signal

   The direction signal determines if the counter increments or decrements its value.

2. Step 2: Relate direction to counting behavior

   If direction is high, the counter counts up; if low, it counts down.

3. Final Answer:

   Whether the counter counts up or down -> Option C

4. Quick Check:

   Direction controls count direction = C [OK]

Hint: Direction signal decides count up or down [OK]

Common Mistakes:

• Confusing direction with clock speed
• Thinking reset controls counting direction
• Assuming direction changes output width

2. Which of the following is the correct Verilog syntax to declare a 4-bit up-down counter with direction input?

easy

A. wire [4:0] count; input direction; always @(negedge clk) begin if(reset) count = 0; else if(direction) count = count + 1; else count = count - 1; end

B. reg [3:0] count; input dir; always @(posedge clk) begin if(reset) count <= 0; else if(dir) count <= count + 1; else count <= count - 1; end

C. reg [3:0] count; input dir; always @(posedge clk) begin if(reset) count = 0; else if(dir) count = count + 1; else count = count - 1; end

D. reg [3:0] count; input dir; always @(posedge clk) begin if(reset) count <= 0; else if(dir) count <= count - 1; else count <= count + 1; end

Solution

1. Step 1: Check variable declarations and types

   Count should be a 4-bit reg, direction input is 'dir'.

2. Step 2: Verify always block and assignments

   Use posedge clk, non-blocking assignments '<=' for sequential logic, reset sets count to 0, dir controls increment or decrement.

3. Final Answer:

   Correct syntax with reg, posedge clk, non-blocking assignments, and direction control -> Option B

4. Quick Check:

   Proper reg and non-blocking assignments = A [OK]

Hint: Use reg, posedge clk, and non-blocking <= for counters [OK]

Common Mistakes:

• Using wire instead of reg for count
• Using blocking '=' in sequential always block
• Incorrect clock edge sensitivity
• Reversing increment and decrement logic

3. Given this Verilog code snippet for a 3-bit up-down counter with direction control:

reg [2:0] count = 3'b000;
always @(posedge clk) begin
  if(reset) count <= 3'b000;
  else if(dir) count <= count + 1;
  else count <= count - 1;
end

If reset=0, dir=1, and the clock pulses 5 times starting from 0, what is the value of count after 5 pulses?

medium

A. 3'b101

B. 3'b111

C. 3'b100

D. 3'b110

Solution

1. Step 1: Understand initial conditions and direction

   Count starts at 0, reset is inactive, dir=1 means count up.

2. Step 2: Calculate count after 5 increments

   Counting up 5 times from 0: 0->1->2->3->4->5, which is 3'b101 in binary.

3. Final Answer:

   3'b101 -> Option A

4. Quick Check:

   0 + 5 increments = 5 (binary 101) [OK]

Hint: Count up adds 1 each clock pulse [OK]

Common Mistakes:

• Forgetting initial count is zero
• Confusing binary values
• Counting down instead of up

4. Identify the error in this Verilog code for an up-down counter:

reg [3:0] count;
always @(posedge clk) begin
  if(reset) count = 0;
  else if(dir) count <= count + 1;
  else count <= count - 1;
end

medium

A. Using blocking assignment '=' for reset inside always block

B. Missing sensitivity to negedge clk

C. Count should be declared as wire, not reg

D. Direction signal 'dir' is not declared

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic requires non-blocking assignments '<=' for all assignments inside always @(posedge clk).

2. Step 2: Identify inconsistent assignment usage

   Reset uses blocking '=' which can cause simulation mismatches; it should use '<=' like other assignments.

3. Final Answer:

   Using blocking assignment '=' for reset inside always block -> Option A

4. Quick Check:

   Use '<=' for all sequential assignments [OK]

Hint: Use non-blocking '<=' in sequential always blocks [OK]

Common Mistakes:

• Mixing blocking and non-blocking assignments
• Ignoring declaration of signals
• Wrong sensitivity list for clock

5. You want to design a 4-bit up-down counter with direction control and synchronous reset in Verilog. The counter should wrap around when it reaches max or min values (i.e., counting up from 15 goes to 0, counting down from 0 goes to 15). Which code snippet correctly implements this behavior?

hard

A. always @(posedge clk) begin
if(reset) count <= 0;
else if(dir) count <= count + 1;
else count <= count - 1;
end

B. always @(posedge clk) begin
if(reset) count <= 0;
else if(dir) count <= (count == 4'b0000) ? 4'b1111 : count - 1;
else count <= (count == 4'b1111) ? 0 : count + 1;
end

C. always @(posedge clk) begin
if(reset) count <= 0;
else if(dir) count <= count - 1;
else count <= count + 1;
end

D. always @(posedge clk) begin
if(reset) count <= 0;
else if(dir) count <= (count == 4'b1111) ? 0 : count + 1;
else count <= (count == 4'b0000) ? 4'b1111 : count - 1;
end

Solution

1. Step 1: Understand wrap-around conditions

   When counting up at max (15), reset to 0; when counting down at 0, reset to 15.

2. Step 2: Check code logic for direction and wrap-around

   always @(posedge clk) begin if(reset) count <= 0; else if(dir) count <= (count == 4'b1111) ? 0 : count + 1; else count <= (count == 4'b0000) ? 4'b1111 : count - 1; end correctly uses conditional operator to wrap count on max and min values based on direction.

3. Final Answer:

   Code with conditional wrap-around for max and min counts -> Option D

4. Quick Check:

   Wrap-around logic matches direction and limits [OK]

Hint: Use conditional operator to wrap count at limits [OK]

Common Mistakes:

• Not wrapping count at max/min values
• Reversing increment and decrement logic
• Using incorrect boundary values