Up-down counter with direction control in Verilog - Step-by-Step Execution

Concept Flow - Up-down counter with direction control

Start

↓

Check direction

↓

Up

↓

Increment

↓

Update counter

↓

Output

↓

End

The counter checks the direction input; if up, it increments the count; if down, it decrements the count, then updates the output.

Execution Sample

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 0;
  else if (dir)
    count <= count + 1;
  else
    count <= count - 1;
end

This code resets the counter or increments/decrements it based on the direction signal at each clock pulse.

Execution Table

Step	reset	dir	count before	Condition	Action	count after	Output
1	1	X	X	reset=1	Reset count to 0	0	0
2	0	1	0	dir=1	Increment count	1	1
3	0	1	1	dir=1	Increment count	2	2
4	0	0	2	dir=0	Decrement count	1	1
5	0	0	1	dir=0	Decrement count	0	0
6	0	1	0	dir=1	Increment count	1	1
7	1	X	1	reset=1	Reset count to 0	0	0

💡 Simulation ends after reset is asserted again at step 7.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7
count	X	0	1	2	1	0	1	0
reset	X	1	0	0	0	0	0	1
dir	X	X	1	1	0	0	1	X

Key Moments - 3 Insights

Why does the count reset to 0 even if dir is 1 or 0?

Because reset has the highest priority in the if-else chain (see step 1 and 7 in execution_table), it resets count regardless of dir.

What happens if dir changes while reset is 0?

The counter increments if dir=1 or decrements if dir=0, as shown in steps 2-6 in execution_table.

Why is count before 'X' at step 1?

At the start, count is undefined (X), but reset sets it to 0 immediately (step 1).

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of count after step 4?

A 2

B 0

C 1

D 3

💡 Hint

Check the 'count after' column at step 4 in execution_table.

At which step does the reset signal cause the count to become 0 again?

A Step 7

B Step 2

C Step 5

D Step 4

💡 Hint

Look for rows where reset=1 and count after=0 in execution_table.

If dir was always 0 and reset never asserted after start, what would happen to count?

A It would keep incrementing

B It would keep decrementing

C It would stay at 0

D It would reset repeatedly

💡 Hint

Refer to variable_tracker and execution_table steps where dir=0 and reset=0.

Concept Snapshot

Up-down counter with direction control in Verilog:
- Use always block triggered by posedge clk or reset
- If reset=1, count=0 (highest priority)
- Else if dir=1, count increments
- Else count decrements
- Output count value each clock cycle

Full Transcript

This visual execution trace shows an up-down counter in Verilog controlled by a direction signal and reset. The counter resets to zero when reset is high. When reset is low, if direction is high, the counter increments by one each clock cycle; if direction is low, it decrements by one. The execution table tracks each step with signals and count values. Variable tracker shows how count, reset, and dir change over time. Key moments clarify priority of reset and behavior of direction. The quiz tests understanding of count values at specific steps and effects of signals.