Up-down counter with direction control in Verilog - Mini Project: Build & Apply

Up-down counter with direction control

📖 Scenario: You are designing a simple digital circuit that counts numbers up or down based on a control signal. This is useful in many electronics projects like timers, clocks, or simple user interfaces.

🎯 Goal: Create a Verilog module for an up-down counter that changes its count direction based on a control input signal.

📋 What You'll Learn

Create a 4-bit register to hold the count value

Use a clock input to update the count on each rising edge

Use a direction input signal to decide whether to count up or down

Reset the count to zero when reset signal is active

💡 Why This Matters

🌍 Real World

Up-down counters are used in digital clocks, volume controls, and event counters where counting direction changes dynamically.

💼 Career

Understanding counters and direction control is fundamental for hardware design engineers working with digital circuits and FPGA programming.

1

Create the module and declare inputs and outputs

Write a Verilog module named up_down_counter with inputs clk, reset, and dir, and a 4-bit output count. Declare count as a reg type.

Verilog

module up_down_counter(input clk, input reset, input dir, output reg [3:0] count);
// Your code here
endmodule

Need a hint?

Start by declaring the module and its ports exactly as described.

2

Initialize the count register

Inside the module, declare an always block triggered on the rising edge of clk or when reset is high. Inside it, set count to 0 when reset is high.

Verilog

module up_down_counter(input clk, input reset, input dir, output reg [3:0] count);

always @(posedge clk or posedge reset) begin
    // Your code here
end

endmodule

Need a hint?

Use an asynchronous reset inside the always block to set count to zero.

3

Add counting logic based on direction

Inside the always block, add an else branch after the reset condition. Use an if statement to check if dir is 1. If yes, increment count by 1. Otherwise, decrement count by 1.

Verilog

module up_down_counter(input clk, input reset, input dir, output reg [3:0] count);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 4'b0000;
    end else begin
        // Your code here
    end
end

endmodule

Need a hint?

Use nested if-else inside the always block to update count based on dir.

4

Test the counter output

Add a initial block to display the value of count every time it changes using $monitor. This will help you see the counter output during simulation.

Verilog

module up_down_counter(input clk, input reset, input dir, output reg [3:0] count);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 4'b0000;
    end else begin
        if (dir) begin
            count <= count + 1;
        end else begin
            count <= count - 1;
        end
    end
end

// Your code here
endmodule

Need a hint?

Use $monitor inside an initial block to print count changes during simulation.