Up-down counter with direction control in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 3-bit up-down counter with direction control

What is the value of count after 5 clock cycles if dir = 1 (count up) starting from 3'b010?

Verilog

module counter(input clk, input dir, output reg [2:0] count);
  initial count = 3'b010;
  always @(posedge clk) begin
    if (dir)
      count <= count + 1;
    else
      count <= count - 1;
  end
endmodule

A 3'b101

B 3'b111

C 3'b100

D 3'b000

💡 Hint

Count up 5 times starting from 2 (binary 010).

Starting at 3'b010 (decimal 2), counting up 5 times: 3,4,5,6,7 which is 3'b111. But since counting starts after first clock, after 5 cycles count is 7 (3'b111). However, initial count is 2, after 5 increments count is 7 (3'b111). So correct answer is 3'b111.

❓ Predict Output

intermediate

Output of a 4-bit up-down counter counting down

Given a 4-bit up-down counter starting at 4'b1001 and dir = 0 (count down), what is the value of count after 3 clock cycles?

Verilog

module counter(input clk, input dir, output reg [3:0] count);
  initial count = 4'b1001;
  always @(posedge clk) begin
    if (dir)
      count <= count + 1;
    else
      count <= count - 1;
  end
endmodule

A 4'b0110

B 4'b0111

C 4'b1000

D 4'b0101

💡 Hint

Count down 3 times starting from 9 (binary 1001).

Starting at 4'b1001 (decimal 9), counting down 3 times: 8,7,6 which is 4'b0110.

🔧 Debug

advanced

Identify the error in this up-down counter code

What error will this Verilog code produce when simulated?

Verilog

module counter(input clk, input dir, output reg [2:0] count);
  initial count = 3'b000;
  always @(posedge clk) begin
    if (dir == 1)
      count <= count + 1;
    else
      count <= count - 1;
  end
endmodule

A Synthesis error: blocking assignment used in sequential always block

B Runtime error: count overflows without warning

C No error, code runs correctly

D Syntax error: missing semicolon

💡 Hint

Check the type of assignment used inside the always block triggered by clock.

In sequential logic (posedge clk), non-blocking assignments (<=) should be used instead of blocking (=). Using blocking assignment here causes synthesis issues.

🧠 Conceptual

advanced

Behavior of up-down counter at overflow

What happens when a 3-bit up-down counter with direction control counts up from 3'b111 (decimal 7) and increments once more?

A Simulation error due to overflow

B Count stays at 3'b111 (saturates)

C Count becomes 3'b1000 (4 bits)

D Count wraps around to 3'b000

💡 Hint

Think about how binary counters behave with fixed bit width.

A 3-bit counter wraps around after reaching max value 7 (3'b111). Incrementing 7 + 1 results in 0 (3'b000).

📝 Syntax

expert

Identify the syntax error in this up-down counter code

Which option correctly fixes the syntax error in this Verilog code snippet?

Verilog

always @(posedge clk) begin
  if (dir == 1)
    count <= count + 1
  else
    count <= count - 1;
end

A Change 'begin' to 'begin:'

B Replace '==' with '=' in the if condition

C Add semicolon after 'count <= count + 1;'

D Remove 'else' keyword

💡 Hint

Check statement termination inside always block.

Verilog statements must end with semicolons. Missing semicolon after 'count <= count + 1' causes syntax error.